SLAAED5 june   2023 AFE11612-SEP , INA240-SEP , OPA4H199-SEP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 LDMOS and GaN Power Amplifier FET PA Basics
  5. 2 VGS Compensation
  6. 3 Sequencing
  7. 4 An Integrated PA Biasing Solution
  8. 5 Negative GaN Biasing
  9. 6 VDRAIN Switching Circuit
  10. 7 Controlled Gate Sequencing Circuit
  11. 8 VDRAIN Monitoring
  12. 9 IDQ Monitoring
  13. 10External Negative Power Supply Monitoring
  14. 11PA Temperature Monitoring
  15. 12Summary
  16. 13References

8 VDRAIN Monitoring

It is important to monitor the VDRAIN voltage to ensure the PA Drain supply is operating at the expected voltage. A resistor divider is required to properly scale the VDRAIN voltage, as the voltage range for the ADC is selected to be 0 V to 2.5 V or 0 V to 5 V. This can be accomplished using the integrated successive-approximation register (SAR) ADC in the AFE11612-SEP. SAR ADCs have an internal sampling capacitor which must be charged every time there is an ADC conversion. This capacitor must be charged within the sample acquisition time to ensure the ADC measures the voltage correctly. This is done using a charge-bucket filter with an external capacitor (CFILT) of approximately 1nF. The impedance of the resistor divider must be limited, ideally under 10 kΩ to allow sufficient current to charge the sampling capacitor.

GUID-20230608-SS0I-H6XQ-W7HT-H2KBMLJPWQWZ-low.svgFigure 8-1 VDRAIN Monitor Circuit