SLLSEL2C September   2015  – July 2016 SN65DP149 , SN75DP149

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 HPD Switching Characteristics
    12. 7.12 DDC and I2C Switching Characteristics
    13. 7.13 Parameter Measurement Information
    14. 7.14 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reset Implementation
      2. 8.3.2 Operation Timing
      3. 8.3.3 Input Lane Swap and Polarity Working
      4. 8.3.4 Main Link Inputs
      5. 8.3.5 Main Link Inputs Debug Tools
      6. 8.3.6 Receiver Equalizer
      7. 8.3.7 Termination Impedance Control
      8. 8.3.8 TMDS Outputs
        1. 8.3.8.1 Pre-Emphasis/De-Emphasis
    4. 8.4 Device Functional Modes
      1. 8.4.1 Retimer Mode
      2. 8.4.2 Redriver Mode
      3. 8.4.3 DDC Functional Description
    5. 8.5 Register Maps
      1. 8.5.1 DP-HDMI Adaptor ID Buffer
      2. 8.5.2 Local I2C Interface Overview
      3. 8.5.3 I2C Control Behavior
      4. 8.5.4 I2C Control and Status Registers
        1. 8.5.4.1 Bit Access Tag Conventions
        2. 8.5.4.2 CSR Bit Field Definitions
          1. 8.5.4.2.1 ID Registers
          2. 8.5.4.2.2 Misc Control
          3. 8.5.4.2.3 HDMI Control
          4. 8.5.4.2.4 Equalization Control Register
          5. 8.5.4.2.5 EyeScan Control Register
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Use Case of SNx5DP149
      2. 9.1.2 DDC Pullup Resistors
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Example
      1. 9.3.1 Compliance Testing
  10. 10Power Supply Recommendations
    1. 10.1 Power Management
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

11 Layout

11.1 Layout Guidelines

TI recommends to use at a minimum a four layer stack up to accomplish a low-EMI PCB design. TI recommends six layers because the SNx5DP149 is a two voltage rail device.

  • Routing the high-speed input DisplayPort traces and TMDS output traces on the top layer avoids the use of vias (and their discontinuities) and allows for clean interconnects from the HDMI connectors to the repeater inputs and from the repeater output to the subsequent receiver circuit. It is important to match the electrical length of these high speed traces to minimize both inter-pair and intra-pair skew.
  • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
  • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance.
  • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.
  • If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high- frequency bypass capacitance significantly.
  • The control pin pullup and pulldown resistors are shown in application section for reference. If a high is needed only use the pull up. If a low is needed only use the pull down. If mid level is to be selected do not use either resistors and leave the pin floating/No connect.
SN65DP149 SN75DP149 layout_stack_LLSEJ2.gif Figure 32. Recommended 4- or 6-Layer Stack for a Receiver PCB Design

11.2 Layout Example

SN65DP149 SN75DP149 sllsej2_figure36.gif Figure 33. Layout Example for the DP149RSB

11.3 Thermal Considerations

On a high-K board: TI recommends to solder the PowerPAD™ onto the thermal land. A thermal land is the area of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the SNx5DP149 device can operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias.

On a low-K board: For the device to operate across the temperature range on a low-K board, a 1-oz Cu trace connecting the GND pins to the thermal land must be used. A simulation shows RθJA = 100.84°C/W allowing 545-mW power dissipation at 70°C ambient temperature.

A general PCB design guide for PowerPAD packages is provided in PowerPAD Thermally Enhanced Package, SLMA002.