SLLSF61C
December 2019 – June 2022
TLIN2021-Q1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Thermal Information
7.4
Recommended Operating Conditions
7.5
Power Supply Characteristics
7.6
Electrical Characteristics
7.7
AC Switching Characteristics
7.8
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
LIN
9.3.1.1
LIN Transmitter Characteristics
9.3.1.2
LIN Receiver Characteristics
9.3.1.2.1
Termination
9.3.2
TXD
9.3.3
RXD
9.3.4
VSUP
9.3.5
GND
9.3.6
EN
9.3.7
WAKE
9.3.8
INH
9.3.9
Local Faults
9.3.10
TXD Dominant Time-Out (DTO)
9.3.11
Bus Stuck Dominant System Fault: False Wake-Up Lockout
9.3.12
Thermal Shutdown
9.3.13
Under Voltage on VSUP
9.3.14
Unpowered Device
9.4
Device Functional Modes
9.4.1
Normal Mode
9.4.2
Sleep Mode
9.4.3
Standby Mode
9.4.4
Wake-Up Events
9.4.4.1
Local Wake-Up (LWU) via WAKE Input Terminal
9.4.4.2
Wake-Up Request (RXD)
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedures
10.2.2.1
Normal Mode Application Note
10.2.2.2
TXD Dominant State Time-Out Application Note
10.2.3
Application Curves
10.3
Power Supply Recommendations
Layout
10.4.1
Layout Guidelines
10.4.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
8
Parameter Measurement Information
Figure 8-1
Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10
Figure 8-2
RX Response: Operating Voltage Range
Figure 8-3
LIN Bus Input Signal
Figure 8-4
LIN Receiver Test with RX access Param 17, 18, 19, 20
Figure 8-5
V
SUP_NON_OP
Param
11
54/56
Figure 8-6
Test Circuit for I
BUS_LIM
at Dominant State (Driver on) Param 12
Figure 8-7
Test Circuit for I
BUS_PAS_dom
; TXD = Recessive State V
BUS
= 0 V, Param 13
Figure 8-8
Test Circuit for I
BUS_PAS_rec
Param 14
Figure 8-9
Test Circuit for I
BUS_NO_GND
Loss of GND
Figure 8-10
Test Circuit Slope Control and Duty Cycle Param
27, 28, 29, 30
, 72, 73, 74, 75
Figure 8-11
Definition of Bus Timing Parameters
Figure 8-12
Propagation Delay Test Circuit; Param 31, 32
Figure 8-13
Propagation Delay
Figure 8-14
Mode Transitions
Figure 8-15
Wake-up Through EN
Figure 8-16
Wake-up through LIN