SLLU149E June   2011  – February 2016 TUSB7320 , TUSB7340

 

  1.   TUSB73x0 Board Design and Layout Guidelines
    1.     Trademarks
    2.     Related Documentation
  2. 1 Typical System Implementation
    1. 1.1 Overview
  3. 2 Power
    1. 2.1 Overview
    2. 2.2 Digital Supplies
    3. 2.3 Analog Supplies
    4. 2.4 Ground Terminal
    5. 2.5 Capacitor Selection Recommendations
    6. 2.6 USB VBUS
  4. 3 Device Reset
    1. 3.1 Overview
  5. 4 General High Speed Layout Guidelines
    1. 4.1 Printed Circuit Board Stackup (FR-4 Example)
    2. 4.2 Return Current and Plane References
    3. 4.3 Split Planes – What to Avoid
    4. 4.4 Avoiding Crosstalk
  6. 5 USB Connection
    1. 5.1 Overview
    2. 5.2 Internal Chip Trace Length Mismatch
    3. 5.3 High-Speed Differential Routing
    4. 5.4 SuperSpeed Differential Routing
  7. 6 Package and Breakout
    1. 6.1 Package Drawing
    2. 6.2 Routing Between Pads
    3. 6.3 Pads
    4. 6.4 Land Pattern Recommendation
    5. 6.5 Solder Stencil
  8. 7 PCI Express Connection
    1. 7.1 Internal Chip Trace Length Mismatch
    2. 7.2 Transmit and Receive Links
    3. 7.3 PCI-Express Reference Clock Input
    4. 7.4 PCI Express Reset
    5. 7.5 PCI Express WAKE/CLKREQ
      1. 7.5.1 Leakage Current on Pins WAKE# and CLKREQ#
      2. 7.5.2 Recommendations
  9. 8 Wake from S3
    1. 8.1 Overview
  10. 9 Device Input Clock
    1. 9.1 Overview
  11. 10JTAG Interface
    1. 10.1 Overview
  12. 11Differential Pair ESD Protection
    1. 11.1 Overview
  13. 12SuperSpeed Redriver
    1. 12.1 Overview
  14. 13SMI Pin Implementation
    1. 13.1 Overview
  15. 14Schematics
    1. 14.1 Overview
    2. 14.2 TUSB7320 DEMO EVM REVB Schematics
    3. 14.3 TUSB7340 DEMO EVM REVB Schematics
  16.   Revision History

7.2 Transmit and Receive Links

The TUSB73x0 has an x1 PCI Express interface that runs at 5-Gb/s and is fully compliant to the PCI Express Base Specification, Revision 2.0.

The TUSB73x0 TX and RX terminals attach to the upstream PCI Express device over a 5-Gb/s high-speed differential transmit and receive PCI Express x1 Link. The connection details are provided in the following table.

It is permissible to swap the plus and minus on either or both of the PCIe differential pairs. This may be necessary to prevent the differential traces from crossing over one another. However it is not permissible to swap the transmitter differential pair with the receive differential pair.

In order to minimize cross-talk on the PCIe differential signal pair, it is recommended that the spacing between the TX and RX signal pairs for each interface be five times the width of the trace (5W rule). For instance, if the PCIe TX differential pair trace width is 5 mils, then there should be 25 mils of space between the TX and RX differential pairs.

If this 5W rule cannot be implemented, then the space between the TX and RX differential pairs should be maximized as much as possible and ground-fill should be placed between the two. In this case, it is better to route each differential pair on opposite sides of the board with a ground plane between them.

Table 7-2 Transmit and Receive Terminals

TUSB73x0 Terminal Name Upstream PCIe Device
Terminal Name		 Description
TXP RXP TUSB73x0 transmit positive differential terminal connects to the upstream device receive positive differential terminal.
TXP RXN TUSB73x0 transmit negative differential terminal connects to the upstream device receive negative differential terminal.
RXP TXP TUSB73x0 receive positive differential terminal connects to the upstream device transmit positive differential terminal.
RXN TXP TUSB73x0 receive negative differential terminal connects to the upstream device transmit negative differential terminal.

The TUSB73x0 TXP and TXN terminals comprise a low-voltage, 100-Ω differential signal pair. The RXP and RXN terminals for the TUSB73x0 receive a low-voltage, 100-Ω differential signal pair. The TUSB73x0 has integrated 50-Ω termination resistors to VSS on both the RXP and RXN terminals eliminating the need for external components.

The TX lane of the differential signal pair must be ac-coupled. The recommended value for the series capacitor is 0.1 μF. To minimize stray capacitance associated with the series capacitor circuit board solder pads, 0402 sized capacitors are recommended.

When routing a 5-Gb/s low-voltage, 100-Ω differential signal pair, the following circuit board design guidelines must be considered:

  1. The PCI-Express drivers and receivers are designed to operate with adequate bit error rate margins over a 20-inch maximum length signal pair routed through FR4 circuit board material.
  2. Each differential signal pair must have a 100-Ω differential impedance, with each single-ended lane measuring in the range of 50-Ω to 55-Ω impedance to ground.
  3. The differential signal trace lengths associated with a PCI Express high-speed link must be length matched to minimize signal jitter. This length matching requirement applies only to the P and N signals within a differential pair. The transmitter differential pair does not need to be length matched to the receiver differential pair. The absolute maximum trace length difference between the TXP signal and TXN signal must be less than 5 mils. This also applies to the RXP and RXN signal pair.
  4. If a differential signal pair is broken into segments by vias, series capacitors, or connectors, the length of the positive signal trace must be length matched to the negative signal trace for each segment. Trace length differences over all segments are additive and must be less than 5 mils.
  5. The location of the series capacitors is critical. For add-in cards, the series capacitors are located between the TXP/TXN terminals and the PCI-Express connector. In addition, the capacitors are placed near the PCI Express connector. This translates to two capacitors on the motherboard for the downstream link and two capacitors on the add-in card for the upstream link. If both the upstream device and the downstream device reside on the same circuit board, the capacitors are located near the TXP/TXN terminals for each link.
  6. The number of vias must be minimized. Each signal trace via reduces the maximum trace length by approximately 2 inches. For example: if 6 vias are needed, the maximum trace length is 8 inches.
  7. When routing a differential signal pair, 45° angles are preferred over 90° angles. Signal trace length matching is easier with 45° angles and overall signal trace length is reduced.
  8. The differential signal pairs must not be routed over gaps in the power planes or ground planes. This causes impedance mismatches.
  9. If vias are used to change from one signal layer to another signal layer, it is important to maintain the same 50-Ω impedance reference to the ground plane. Changing reference planes causes signal trace impedance mismatches. If changing reference planes cannot be prevented, bypass capacitors connecting the two reference planes next to the signal trace vias will help reduce the impedance mismatch.
  10. If possible, the differential signal pairs must be routed on the top and bottom layers of a circuit board. Signal propagation speeds are faster on external signal layers.