SLUAAH0 February   2022 UCC14130-Q1 , UCC14131-Q1 , UCC14140-Q1 , UCC14141-Q1 , UCC14240-Q1 , UCC14241-Q1 , UCC14340-Q1 , UCC14341-Q1 , UCC15240-Q1 , UCC15241-Q1

 

  1.   Trademarks
  2. 1 Introduction
    1. 1.1 Pin Configuration and Functions
  3. 2 Three-Phase Traction Inverter
  4. 3 Gate Drive Bias Requirements
    1. 3.1 Gate Drive Bias Architectures
    2. 3.2 IGBT vs. SiC
    3. 3.3 Determining Required Bias Supply Power
    4. 3.4 Input Voltage Requirements
    5. 3.5 Output Voltage Requirements
  5. 4 Single Positive Isolated Output Voltage
  6. 5 Dual Positive and Negative Output Voltages
  7. 6 Dual Positive Output Voltages
  8. 7 Capacitor Selection
  9. 8 RLIM Current Limit Resistor
    1. 8.1 RLIM Functional Description
    2. 8.2 RLIM Dual Output Configuration
      1. 8.2.1 CVEE Above Nominal Value CVDD Below Nominal Value
      2. 8.2.2 CVEE Below Nominal Value CVDD Above Nominal Value
      3. 8.2.3 Gate Driver Quiescent Current: IQ_VEE > IQ_VDD
      4. 8.2.4 Gate Driver Quiescent Current: IQ_VEE < IQ_VDD
      5. 8.2.5 CVEE Above Nominal Value CVDD Below Nominal Value: IQ_VEE > IQ_VDD
      6. 8.2.6 CVEE Below Nominal Value CVDD Above Nominal Value: IQ_VEE < IQ_VDD
    3. 8.3 RLIM Single Output Configuration
  10. 9 UCC14240-Q1 Excel Design Calculator Tool
  11. 10Thermal Considerations
    1. 10.1 Thermal Resistance
    2. 10.2 Junction-to-Top Thermal Characterization Parameter
    3. 10.3 Thermal Measurement and TJ Calculation Example
  12. 11Enable (ENA) and Power Good (/PG)
  13. 12PCB Layout Considerations
  14. 13Reference Design Example
  15. 14Summary
  16. 15References

8.2.2 CVEE Below Nominal Value CVDD Above Nominal Value

The second case shown in Figure 8-2 illustrates the RLIM regulator sinking current from the gate driver COM pin to compensate for the nominal values of CVEE being lower and CVDD being higher. In this case the voltage across CVEE (COM-VEE) drifts higher resulting in ILIM sinking current through RLIM to restore equal capacitor charge balance.



Figure 8-2 Case 2: ILIM Sinking, CVEE Lower, CVDD Higher

The additional compensated charge, ΔQC_DN, as a result of the worst case expected capacitor variation ΔCVDD and ΔCVEE is given by Equation 24.

Equation 24. ∆QC_DN=QG×CVDD×(1-∆CVDD)CVDD×1-∆CVDD+CVEE×1-∆CVEE-CVDDCVDD+CVEE

The product of ΔQC_DN and FSW can then be used to determine the ILIM source current given by Equation 25.

Equation 25. ILIM=∆QC_DN×FSW

RLIM is then determined by Equation 26 as.

Equation 26. RLIM=VDD-COMILIM-RINT_DN