SLVAF93A october   2022  – april 2023 LP8764-Q1 , TPS6594-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Hardware and PMIC Setup
  5. 3Configuration Overview
  6. 4Instructions
  7. 5Special Considerations
    1. 5.1 Changing the Serial Control Interface
    2. 5.2 Updating the Frequency Selection
    3. 5.3 PFSM
    4. 5.4 Permanently Locking the NVM
    5. 5.5 Updating the Register CRC
  8. 6NVM Validation
  9. 7References
  10.   A Registers Backed by NVM
  11.   B Non-NVM Registers Which are Part of the Register CRC
  12.   C CRC for User Registers, Page 0 and Page 4
  13.   D Example With I2C Serial Interface
  14.   E Revision History

3 Configuration Overview

The PMIC has two memory spaces, the register map space and the NVM space. As Figure 3-1 shows, configuring the NVM is done by first writing to the register map through the serial interface and then copying the contents to the NVM. Because the configuration first involves writing to the register map, which controls the regulators and GPIO, there must be no dependency or need to use the PMIC resources. For example, in the PDN-0B implementation(4) the VIO is supplied by a load switch which is controlled by the PMIC GPIO. The dependency upon the GPIO output prohibits NVM configuration since the GPIO controls the VIO, impacting the I2C and corrupting the configuration. In contrast, the TPS6594 EVM(5) provides an independent supply for VIO.

GUID-20211013-SS0I-ZG34-VCBV-NRCKJKJ8HPDJ-low.svg Figure 3-1 Register Map Memory and NVM Spaces