SLVK158 November 2023 TPS7H6003-SP
PRODUCTION DATA
The TPS7H6003-SP is fabricated in the TI Linear BiCMOS 250-nm process with a 4LM back-end-of-line (BEOL) stack. The total stack height from the surface of the passivation to the silicon surface is 9.8 μm based on nominal layer thickness as shown in Figure 5-1. Accounting for energy loss through the 1-mil thick Aramica beam port window, the 40-mm air gap, and the BEOL stack over the TPS7H6003-SP, the effective LET (LETEFF) at the surface of the silicon substrate and the depth was determined with the SEUSS 2020 Software (provided by the Texas A&M Cyclotron Institute and based on the latest SRIM-2013 [7] models). The results are shown in Ion LETEFF, Depth, and Range in SiliconIon LETEFF, Depth, and Range in SiliconIon LETEFF, Depth, and Range in Silicon.
Ion Type | Beam Energy (MeV / nucleon) | Angle of Incidence | Degrader Steps (Number) | Degrader Angle | Range in Silicon (µm) | LETEFF (MeV × cm2/ mg) |
---|---|---|---|---|---|---|
109Ag | 15 | 0 | 0 | 0 | 95.1 | 48 |
141Pr | 15 | 0 | 0 | 0 | 100.8 | 65 |
165Ho | 15 | 0 | 0 | 0 | 97.2 | 75 |