SLVS839H July   2008  – October 2023 TPS54331

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Voltage Reference (VREF)
      3. 7.3.3  Bootstrap Voltage (BOOT)
      4. 7.3.4  Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)
      5. 7.3.5  Programmable Slow Start Using SS Pin
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Slope Compensation
      8. 7.3.8  Current-Mode Compensation Design
      9. 7.3.9  Overcurrent Protection and Frequency Shift
      10. 7.3.10 Overvoltage Transient Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Eco-mode
      2. 7.4.2 Operation With VIN < 3.5 V
      3. 7.4.3 Operation With EN Control
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Output Voltage Set-Point
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Output Filter Components
          1. 8.2.2.5.1 Inductor Selection
        6. 8.2.2.6  Capacitor Selection
        7. 8.2.2.7  Compensation Components
        8. 8.2.2.8  Bootstrap Capacitor
        9. 8.2.2.9  Catch Diode
        10. 8.2.2.10 Output Voltage Limitations
        11. 8.2.2.11 Power Dissipation Estimate
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Electromagnetic Interference (EMI) Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Custom Design with WEBENCH® Tools
    2. 9.2 Support Resources
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

8.2.2.7 Compensation Components

The external compensation used with the TPS54331 device allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric are supported. The design example uses ceramic X5R dielectric output capacitors, but other types are supported.

A Type II compensation scheme is recommended for the TPS54331 device. The compensation components are selected to set the desired closed-loop crossover frequency and phase margin for output filter components. The Type II compensation has the following characteristics: a DC gain component, a low-frequency pole, and a mid-frequency zero-pole pair.

Use Equation 16 to calculate the DC gain.

Equation 16. G D C = V G G M × V R E F V O

where

  • VGGM is 800.
  • VREF is 0.8 V.

Use Equation 17 to calculate the low-frequency pole.

Equation 17. F P O = 1 2 × π × R O O × C Z

Use Equation 18 to calculate the mid-frequency zero.

Equation 18. F Z 1 = 1 2 × π × R Z × C Z

Use Equation 19 to calculate the mid-frequency pole.

Equation 19. F P 1 = 1 2 × π × R Z × C P

The first step is to select the closed-loop crossover frequency. In general, the closed-loop crossover frequency must be less than 1/8 of the minimum operating frequency. However, for the TPS54331 device, not exceeding 25 kHz for the maximum closed-loop crossover frequency is recommended. The second step is to calculate the required gain and phase boost of the crossover network. By definition, the gain of the compensation network must be the inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is much higher than the closed-loop crossover frequency, the gain of the modulator and output filter can be approximated by Equation 20.

Equation 20. G a i n = - 20 × l o g 2 × π × R S E N S E × F C O × C O

where

  • RSENSE is 1 Ω / 12.
  • FCO is the closed-loop crossover frequency.
  • CO is the output capacitance.

Use Equation 21 to calculate the phase loss.

Equation 21. P L = α × t a n 2 × π × F C O × R E S R × C O -   α × t a n 2 × π × F C O × R O × C O

where

  • RESR is the equivalent series resistance of the output capacitor.
  • RO is VO / IO.

The measured overall loop-response for the circuit is given in Figure 8-7. The actual closed-loop crossover frequency is higher than intended at approximately 25 kHz, which is primarily because variation in the actual values of the output filter components and tolerance variation of the internal feedforward gain circuitry. Overall, the design has greater than 60 degrees of phase margin and is completely stable over all combinations of line and load variability.

Now that the phase loss is known, the required amount of phase boost to meet the phase margin requirement can be determined. Use Equation 22 to calculate the required phase boost.

Equation 22. P B = P M - 90 d e g - P L

where

  • PM is the desired phase margin.

A zero-pole pair of the compensation network is placed symmetrically around the intended closed-loop frequency to provide maximum phase boost at the crossover point. The amount of separation can be calculated with Equation 23. Use Equation 24 and Equation 25 to calculate the resultant zero and pole frequencies.

Equation 23. k = t a n P B 2 + 45 d e g
Equation 24. F Z 1 = F C O k
Equation 25. F P 1 = F C O × k

The low-frequency pole is set so that the gain at the crossover frequency is equal to the inverse of the gain of the modulator and output filter. Because of the relationships established by the pole and zero relationships, use Equation 26 to calculate the value of RZ.

Equation 26. R Z = 2 × π × F C O × V O × C O × R O A G M C O M P × V G G M × V R E F

where

  • VO is the output voltage.
  • CO is the output capacitance.
  • FCO is the desired crossover frequency.
  • ROA is 8 MΩ.
  • GMCOMP is 12 A/V.
  • VGGM is 800.
  • VREF is 0.8 V.

With the value of RZ known, use Equation 27 and Equation 28 to calculate the values of CZ and CP.

Equation 27. C Z = 1 2 × π × F Z 1 × R Z
Equation 28. C P = 1 2 × π × F P 1 × R Z

For this design, the two 47-μF output capacitors are used. For ceramic capacitors, the actual output capacitance is less than the rated value when the capacitors have a DC bias voltage applied, which occurs in a DC-DC converter. The actual output capacitance can be as low as 54 μF. The combined ESR is approximately 0.001 Ω.

Using Equation 20 and Equation 21, the output stage gain and phase loss are equivalent as:

  • Gain = –2.26 dB
  • PL = –83.52 degrees

For 70 degrees of phase margin, Equation 22 requires 63.52 degrees of phase boost.

Use Equation 23, Equation 24, and Equation 25 to calculate the zero and pole frequencies of the following values:

  • FZ1 = 5883 Hz
  • FP1 = 106200 Hz

Use Equation 26, Equation 27, and Equation 28 to calculate the values of RZ, CZ, and CP.

Equation 29. R Z = 2 × π × 25000 × 3.3 × 54 × 10 - 6 × 8 × 10 6 12 × 800 × 0.8 = 29.2 k Ω
Equation 30. C Z = 1 2 × π × 6010 × 29200 = 928 p F
Equation 31. C P = 1 2 × π × 103900 × 29200 = 51 p F

Referring to Figure 8-1 and using standard values for R3, C6, and C7, the calculated values are as follows:

  • R3 = 29.4 kΩ
  • C6 = 1000 pF
  • C7 = 47 pF