SLVU135A June   2005  – June 2021 TPS62110

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification
    3. 1.3 Modifications
      1. 1.3.1 Adjustable Output IC U1 Operation
      2. 1.3.2 Fixed Output Operation
  3. 2Setup
    1. 2.1 Input / Output Connector Descriptions
    2. 2.2 Setup
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
  6. 5Related Documentation From Texas Instruments
  7. 6Revision History

2.1 Input / Output Connector Descriptions

J1–VINPositive input connection from the input supply for U1
J2–GNDReturn connection from the input supply for U1, common with J4.
J3–VOUTOutput voltage connection
J4–GNDOutput return connection, common with J2
J5–LBO/PGLow battery output (LBO) pulled up to Vout; low indicates LBI is below its threshold.
Power good (PG), low indicates output voltage is less than 98.4% of the normal value.
JP1–SYNC PFM/PWMInput for synchronization to external clock signal. High forces low-noise PWM mode, low enables power save PFM/PWM mode.
JP2–ENEnable pin, low on the EN turns unit off.