4.9 Current Sharing

One important consideration when operating devices in parallel configuration is how the total current is shared among the converters. Designers of such parallel systems want to ensure that each converter remains within the recommended operating conditions of the data sheet while also considering worst case conditions. Ensuring this is not a trivial task but can be achieved through various approaches. The most straight forward approach, and the one resulting in the most conservative design, is to take the worst case condition and apply it to all converters regardless of the statistical improbability of such an occurrence. Another approach is to characterize the devices in a parallel system allowing designers to eliminate a signficant amount of variation by having an understanding of the baseline starting point under nominal conditions.

Regardless of the approach, an assumption is made that the ouput current of each converter will be proportional to that converter's power stage transconductance (gmps, or COMP to Iswitch gm in the data sheet). Looking at the electrical characteristics table of the data sheet, one can see that this parameter is specified with an approximate tolerance of +/- 28% regardless of temperature. Without applying any practical engineering judgement, this specification says that in order to guarantee that no single converter exceeds the ROC peak current of 18A (assuming 10% current peaking), the nominal design would target ~13.5A. Allowing for lowest gmps (-28%), the design would provide 9.8A per converter. Extrapolating this worst case even further by assuming all four parallel converters would have the lowest gmps value, a 4-channel parallel design would provide ~39A of total load current. One can certainly design with such assumptions and create a very conservative design. However, doing so would ignore the fact that realizing such a worst case implementation is highly improbable.

By characterizing a parallel system through measurements, the tolerance window of +/-28% can be greatly reduced allowing for more optimal design. Figure 15 and Figure 16 shows how current sharing on a 4-Channel design was characterized. The EVM was modified to allow for a current probe to measure the current out of each converter by placing a wire between the PHASE node of the DUT and the output inductors.

The RMS currents of each probe were captured and recorded on the oscilloscope as shown in Figure 17 and Figure 18. Figure 17 shows the individual converter currents when the total e-load current was set to 40A while Figure 18 shows the same for an e-load current of 65A.

Table 3 shows a summary of the measurements for load currents from 15A to 80A. The second column of Table 3 shows the ideal current per converter if matching were perfect. The next four columns show the mean value of current measured for each converter while the last four columns show the deviation from the ideal value as a percentage. It is this data that is invaluable in understanding the true variation within a system. Taking the row in the table for 65A total e-load current as an example, converter SLAVE2 is operating at +9.92% above nominal, while the MASTER converter is operating at -7.53% below nominal current level. With this information, the system can operate at a toal current of 65A while still keeping each converter within the ROC specified, compared to the 39A the design would support assuming worst case for all converters.