SLVUCI4B february   2023  – may 2023 TPS7H5001-SP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2System Design Theory
    1. 2.1  Switching Frequency
    2. 2.2  Leading Edge Blanking
    3. 2.3  Dead Time
    4. 2.4  Enable and UVLO
    5. 2.5  Output Voltage Programing
    6. 2.6  Soft Start
    7. 2.7  Sensing Circuit
    8. 2.8  FAULT Mode
    9. 2.9  HICCUP Mode
    10. 2.10 Slope Compensation
    11. 2.11 Output Capacitance
    12. 2.12 Compensation
  6. 3Test Results
  7. 4Bill of Materials
  8. 5Schematics
  9. 6PCB Layouts
  10. 7References
  11. 8Revision History

1 Introduction

The TPS7H5001-SP EVM uses the TPS7H5001-SP and LMG1210 to create a synchronous buck converter to bring the 12-V intermediate rail into a 1-V rail at 20-A for core voltage rails of space grade FPGAs. The limiter of the output current in the design is the bottom side GaN FET heat. The output current of this design can be increased by adding a second GaN FET in parallel on the bottom side in order to achieve higher than 20-A of output current. Due to the roughly 150-mA peak current capability of the TPS7H5001’s primary switching outputs, the LMG1210 gate driver is used to amplify the current to provide the FET’s of the synchronous buck with sufficient drive. These outputs are not dependent on the TPS7H5001-SP itself, and can be increased or decreased depending on the design.