SLVUCP4 November   2023

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Header Information
    3. 2.3 Jumper Information
    4. 2.4 Push Buttons
    5. 2.5 Debug Information
    6. 2.6 Test Points
    7. 2.7 Configuring the TPS25730EVM
      1. 2.7.1 Minimum Voltage Configuration
      2. 2.7.2 Maximum Voltage Configuration
      3. 2.7.3 Sink Current Configuration
      4. 2.7.4 Complete Example
  8. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  9. 4Additional Information
    1. 4.1 Trademarks

2.2 Header Information

The TPS25730EVM contains two headers: J3 and J4. J3 allows for access to the high voltage internal power path of the TPS25730, PPHV. Additionally, J3 allows for access to the I2Cs lines of the TPS25730, the CAP_MIS, PLUG_FLIP, and DBG_ACC GPIO outputs, and the VBUS pin of the TPS25730. J4 has connections to ground, the four ADCIN pins of the TPS25730, and the PLUG_EVENT GPIO output.

The TPS25730EVM has one terminal block to allow for connection of a load at J1. This enables testing of the TPS25730 under load. The positive wire of the load needs to be connected to the hole closest to the TI logo, and the ground wire of the load needs to be connected to the hole closest to the SW5 switch.