SNAS669E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
The PLL_CALCTRL1 register is described in the following table.
Bit # | Field | Type | Reset | EEPROM | Description |
---|---|---|---|---|---|
[7:1] | RSRVD | - | - | N | Reserved. |
[0] | PLL_LOOPBW | RW | 0 | Y | PLL Loop bandwidth Control. When PLL_LOOPBW is 1 the loop bandwidth of PLL is reduced to 200 Hz (jitter cleaner mode). When PLL_LOOPBW is 0 the loop bandwidth of PLL is set to its normal range (clock generator mode). NOTE: Proper PLL settings must be used (PFD, charge pump, loop filter) with setting the desired value for PLL_LOOPBW. |