SNLS417C MARCH   2013  – July 2016 DS90UB928Q-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  Timing Requirements for the Serial Control Bus
    8. 6.8  Timing Requirements
    9. 6.9  DC and AC Serial Control Bus Characteristics
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Input Equalization
      5. 7.3.5  Common Mode Filter Pin (CMF)
      6. 7.3.6  Power Down (PDB)
      7. 7.3.7  Video Control Signals
      8. 7.3.8  EMI Reduction Features
        1. 7.3.8.1 LVCMOS VDDIO Option
      9. 7.3.9  Built In Self Test (BIST)
        1. 7.3.9.1 BIST Configuration and Status
          1. 7.3.9.1.1 Sample BIST Sequence
        2. 7.3.9.2 Forward Channel and Back Channel Error Checking
      10. 7.3.10 Internal Pattern Generation
        1. 7.3.10.1 Pattern Options
        2. 7.3.10.2 Color Modes
        3. 7.3.10.3 Video Timing Modes
        4. 7.3.10.4 External Timing
        5. 7.3.10.5 Pattern Inversion
        6. 7.3.10.6 Auto Scrolling
        7. 7.3.10.7 Additional Features
      11. 7.3.11 Image Enhancement Features
        1. 7.3.11.1 White Balance
          1. 7.3.11.1.1 LUT Contents
          2. 7.3.11.1.2 Enabling White Balance
        2. 7.3.11.2 Adaptive Hi-FRC Dithering
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Oscillator Output
      14. 7.3.14 Interrupt Pin (INTB / INTB_IN)
      15. 7.3.15 General-Purpose I/O
        1. 7.3.15.1 GPIO[3:0]
        2. 7.3.15.2 GPIO[8:5]
      16. 7.3.16 I2S Audio Interface
        1. 7.3.16.1 I2S Transport Modes
        2. 7.3.16.2 I2S Repeater
        3. 7.3.16.3 I2S Jitter Cleaning
        4. 7.3.16.4 MCLK
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock and Output Status
      2. 7.4.2 FPD-Link Input Frame and Color Bit Mapping Select
      3. 7.4.3 Low Frequency Optimization (LFMODE)
      4. 7.4.4 Mode Select (MODE_SEL)
      5. 7.4.5 Repeater Configuration
        1. 7.4.5.1 Repeater Connections
          1. 7.4.5.1.1 Repeater Fan-Out Electrical Requirements
      6. 7.4.6 Repeater Connections
        1. 7.4.6.1 Repeater Fan-Out Electrical Requirements
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
    6. 7.6 Register Maps
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transmission Media
        2. 8.2.2.2 Display Application
      3. 8.2.3 Application Curves
    3. 8.3 AV Mute PreventionAV Mute Prevention section.
    4. 8.4 OEN Toggling LimitationOEN Toggling Limitation.
  9. Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

10 Layout

10.1 Layout Guidelines

Circuit board layout and stack-up for the LVDS serializer and deserializer devices must be designed to provide low-noise power to the device. Good layout practice also separates high frequency or high-level inputs and outputs to minimize unwanted stray noise, feedback, and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mil) for power / ground sandwiches. This arrangement utilizes the plane capacitance for the PCB power system and has low inductance, which has proven effectiveness especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors must include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 μF to 10 μF. Tantalum capacitors may be in the 2.2 μF to 10 μF range. The voltage rating of the capacitors must be at least 5X the power supply voltage being used.

TI recommends LCC surface mount capacitors due to their smaller parasitic properties. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. TI recommends a large bulk capacitor at the point of power entry, which smooths low frequency switching noise. Connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor increases the inductance of the path. TI recommends a small body size X7R chip capacitor, such as 0603 or 0805, for external bypass. Because a small body sized capacitor has less inductance. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 MHz to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Put in xref to Pin Functions table typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs. This device requires only one common ground plane to connect all device related ground pins.

Use at least a four layer board with a power and ground planes. Locate LVCMOS signals away from the LVDS lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100 Ω are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise will appear as common mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.

At least 9 thermal vias are necessary from the device center DAP to the ground plane. They connect the device ground to the PCB ground plane, as well as conduct heat from the exposed pad of the package to the PCB ground plane. More information on the WQFN package, including PCB design and manufacturing requirements, is provided in AN-1187 Leadless Leadframe Package (LLP) SNOA401.

Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:

Table 11. No Pullback WQFN Stencil Aperture Summary

DEVICE PIN COUNT MKT Dwg PCB I/O Pad Size (mm) PCB PITCH (mm) PCB DAP SIZE (mm) STENCIL I/O
APERTURE (mm)
STENCIL DAP
Aperture (mm)
NUMBER of DAP
APERTURE OPENINGS
DS90UB928Q-Q1 48 RHS0048A 0.25 x 0.4 0.5 5.1 x 5.1 0.25 x 0.6 5.1 x 5.1 1

Figure 46 shows the PCB layout example derived from the layout design of the DS90UB928QEVM evaluation board. The graphic and layout description are used to determine both proper routing and proper solder techniques when designing the Serializer board.

10.1.1 CML Interconnect Guidelines

See Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines SNLA008 and Application Note 905 Transmission Line RAPIDESIGNER Operation and Applications Guide SNLA035 for full details.

  • Use 100 Ω coupled differential pairs
  • Use the S/2S/3S rule in spacings
    • – S = space between the pair
    • – 2S = space between pairs
    • – 3S = space to LVCMOS signal
  • Minimize the number of Vias
  • Use differential connectors when operating above 500 Mbps line speed
  • Maintain balance of the traces
  • Minimize skew within the pair
  • Terminate as close to the TX outputs and RX inputs as possible

Additional general guidance can be found in the LVDS Owner’s Manual (SNLA187).

10.2 Layout Example

DS90UB928Q-Q1 layout_snls417.gif Figure 46. DS90UB928Q-Q1 Deserializer Example Layout
DS90UB928Q-Q1 928 stencil.png Figure 47. 48-Pin WQFN Stencil Example of Via and Opening Placement