SPRACM8A June   2019  – January 2021 OMAP-L132 , OMAP-L132 , OMAP-L138 , OMAP-L138 , TMS320C6742 , TMS320C6742 , TMS320C6746 , TMS320C6746 , TMS320C6748 , TMS320C6748

 

  1.   Trademarks
  2. 1OMAP-L138 Boot Process
    1. 1.1 During Reset
    2. 1.2 After Reset
  3. 2Boot Utilities
    1. 2.1 AISgen
    2. 2.2 Serial Boot and Flash Loading Utility
      1. 2.2.1 Compiling
        1. 2.2.1.1 Under Windows
        2. 2.2.1.2 Under Linux
      2. 2.2.2 Running
        1. 2.2.2.1 Under Windows
        2. 2.2.2.2 Under Linux
      3. 2.2.3 Serial Flasher Options
    3. 2.3 Modifications for Custom Boards
    4. 2.4 Rebuilding and Customization of Boot Utilities
      1. 2.4.1 Download the Flash and Boot Utilities
      2. 2.4.2 Install and Configure the Required Software
        1. 2.4.2.1 Cygwin
        2. 2.4.2.2 Microsoft .NET Framework
      3. 2.4.3 Compiler Tools
        1. 2.4.3.1 Compiler Tools (CODESOURCERY G++ LITE)
        2. 2.4.3.2 C6X Compiler Tools
        3. 2.4.3.3 Newer CCS
      4. 2.4.4 Rebuilding the Serial Flash and Boot Utils Package for a Particular Platform
      5. 2.4.5 Rebuilding the HexAIS Utility for OMAPL13x
  4. 3Boot Examples
    1. 3.1 Booting Binaries
      1. 3.1.1 Description
      2. 3.1.2 Obtaining the Software
      3. 3.1.3 Running
    2. 3.2 Booting DSP Binaries on AM1808/OMAPL138
      1. 3.2.1 Description
      2. 3.2.2 Obtaining the Software
      3. 3.2.3 Running
        1. 3.2.3.1 OMAP-L138 EVM
        2. 3.2.3.2 C6748 EVM
  5. 4Debugging Bootloader
  6. 5OMAP-L138 Boot Benchmarks
    1. 5.1 Host Boot Performance
    2. 5.2 Test Details
      1. 5.2.1 Methodology
      2. 5.2.2 43
      3. 5.2.3 Software
      4. 5.2.4 Hardware
      5. 5.2.5 Discussion
  7. 6OMAP-L138 Bootloader FAQ
  8. 7References
  9.   A Setting c_int00 Using SYS/BIOS
  10.   Revision History

3.2.1 Description

This section provides information on how to boot a DSP executable on Arm-boot devices. A user boot loader (UBL) will run first and is required to wake up the DSP, which will begin execution of the DSP application. The Arm and the DSP programs are combined into a single AIS image that can be flashed and booted directly.

Note:

This section does not apply to AM1808 devices.

A simple test program is used, in which the DSP repeatedly blinks the LEDs on the OMAP-L138 EVM after booting.

This is a very straightforward process, with a few key things to remember:

  • The Arm must set the HOST1CFG register to change the DSP reset vector. This should point to the entry point of the DSP executable, but it can only be set to 1KB boundaries (the bottom 10 bits are reserved and read as 0). Therefore, the linker command file for the DSP application should specifically force the entry point to also be aligned to a 1KB boundary. For this example, a memory region named "entry_point" was created at address 0x80010000, and the section ".text:_c_int00" was assigned to that memory region.
    Note:

    If you are using SYS/BIOS, see Section A for setting c_int00.

  • The and DSP .map files cannot overlap. If both programs use the same memory address, they will overwrite each other and most likely crash. The linker command files should be written to prevent this.
  • For silicon revision 1.0 and 1.1, the KICK registers must be unlocked before writing to the HOST1CFG register. Additionally, for all revisions, the Arm must be in supervisor mode. The SOC design requires the Arm core to be in supervisor mode to configure pin multiplexing (PINMUX) registers. The TI Arm toolchain configures the core in user mode during initialization so the Arm application needs to include a boot.asm source file to change the Arm execution state to supervisor mode . This file should be included in all projects that need to access certain SYSCFG registers and require supervisor mode.
  • If any sections of the DSP memory map are located in DSP L2 RAM (0x11800000), be aware of two things:
    • Make sure all L2 RAM addresses in the DSP linker command file are referenced in the 0x118xxxxx range and not 0x008xxxxx, as they cannot write to the 0x008xxxxx address range
    • Use the "Configure PSC" function of AISGen to enable the DSP LPSC (PSC0,#15). If the DSP megamodule is in reset, the L2 RAM will not be accessible and the section loads will fail. The AISGen CFG file included with this project enables PSC0,#15 by default.