SPRACU8B August   2021  – January 2023 AM68 , AM68 , AM68A , AM68A , AM69 , AM69 , AM69A , AM69A , DRA821U , DRA821U , DRA829V , DRA829V , TDA4VM , TDA4VM

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Features
      1. 1.1.1 Supported Features (version 0.10.0)
      2. 1.1.2 Unsupported Features (version 0.10.0)
    2. 1.2 Spreadsheet Overview
      1. 1.2.1 Input Worksheets
      2. 1.2.2 Output Worksheets
      3. 1.2.3 Other Worksheets
    3. 1.3 Default SDK Configurations
  4. 2Customizing DDR Configuration
    1. 2.1 Config Worksheet
      1. 2.1.1 System Configuration
      2. 2.1.2 Memory Burst Configuration
    2. 2.2 DRAMTiming Worksheet
      1. 2.2.1 Latency Parameters
      2. 2.2.2 Non-Latency Parameters
    3. 2.3 IO Control Worksheet
      1. 2.3.1 Determining IO Settings
      2. 2.3.2 Processor/DDR Controller IO
      3. 2.3.3 DRAM I/O
  5. 3Software Considerations
    1. 3.1 Updating U-Boot
      1. 3.1.1 Updating DDR Register Settings
      2. 3.1.2 Updating Source to Set Available Memory Size
    2. 3.2 Updating RTOS PDK
      1. 3.2.1 Updating DDR Register Settings
  6. 4Troubleshoot Guide
    1. 4.1 Topics/Issues
      1. 4.1.1 Topic 1
      2. 4.1.2 Topic 2
      3. 4.1.3 Topic 3
  7. 5References
  8.   Revision History

2.3.2 Processor/DDR Controller IO

Additional details of each parameter of this section can be found in the list below:

  1. VREF Control: The VREF control parameters impact the reference voltage used for inputs on the processor data (DQ) and strobe (DQS) input/output pins during READ cycles.
    1. Range: This parameter defines the range of reference voltage values available in the succeeding parameter, "% of VDDQ". The recommended configuration for this parameter is "Range 0".
    2. % of VDDQ: This parameter defines the target reference voltage level, as a percentage of the IO voltage, vdds_ddr. The recommended configuration of this parameter is to set to half of the DDR pull-up calibration configuration. As an example, if the DDR pull-up calibration is set to "VDDQ / 3", then this parameter should be set to [(1/3) / 2] = 16.67% of VDDQ.
    Note: The actual reference voltage used during normal operation is determined by the outcome of the VREF training algorithm performed during the initialization of the DDR interface.
  2. Drive Strength: The drive strength parameters impact the voltage swing and signal integrity of the processor DDR pins during WRITE cycles. As discussed in Section 2.3.1, the appropriate value should be selected based on the IO model settings used to achieve the best simulation results. Table 2-1 illustrates the mapping between the IBIS IO model name and the appropriate drive strength parameter value.
    Table 2-1 Jacinto 7 DDR IO Drive Strength to IBIS Model Mapping
    Tool Parameter IO Model (1)(2) Corresponding Parameter Value
    Driver Pull-Up lpddr4_ocd_240p_240n 240 Ω
    lpddr4_ocd_120p_120n 120 Ω
    lpddr4_ocd_80p_80n 80 Ω
    lpddr4_ocd_60p_60n 60 Ω
    lpddr4_ocd_48p_48n 48 Ω
    lpddr4_ocd_40p_40n 40 Ω
    lpddr4_ocd_120pd_60p_40n(3) Not Supported
    lpddr4_ocd_120pd_48p_40n(3) Not Supported
    Driver Pull-Down lpddr4_ocd_240p_240n 240 Ω
    lpddr4_ocd_120p_120n 120 Ω
    lpddr4_ocd_80p_80n 80 Ω
    lpddr4_ocd_60p_60n 60 Ω
    lpddr4_ocd_48p_48n 48 Ω
    lpddr4_ocd_40p_40n 40 Ω
    lpddr4_ocd_120pd_60p_40n(3) Not Supported
    lpddr4_ocd_120pd_48p_40n(3) Not Supported
    (1) Model names based on IBIS file j7es_v0p2.ibs, DRA829 and TDA4VM IBIS File. While the IO model name should be the same across Jacinto 7 processors, the correct processor IBIS model must be used for simulations and can be obtained from the corresponding product home page.
    (2) Model names also used to represent the differential version of the model (models ending in _diff)
    (3) This IO model is not currently supported by the Jacinto 7 DDRSS Register Configuration Tool.
  3. Termination: The termination parameters impact the voltage swing and signal integrity of the processor DDR pins during READ cycles. As discussed in Section 2.3.1, the appropriate value should be selected based on the IO model settings used to achieve the best simulation results. Table 2-2 illustrates the mapping between the IBIS IO model name and the appropriate termination parameter value.
    Table 2-2 Jacinto 7 DDR IO Termination to IBIS Model Mapping
    Tool Parameter IO Model (1)(2) Corresponding Parameter Value
    ODT Pull-Up lpddr4_odt_240 Hi-Z
    lpddr4_odt_120 Hi-Z
    lpddr4_odt_80 Hi-Z
    lpddr4_odt_60 Hi-Z
    lpddr4_odt_48 Hi-Z
    lpddr4_odt_40 Hi-Z
    lpddr4_odt_off Hi-Z
    ODT Pull-Down lpddr4_odt_240 240 Ω
    lpddr4_odt_120 120 Ω
    lpddr4_odt_80 80 Ω
    lpddr4_odt_60 60 Ω
    lpddr4_odt_48 48 Ω
    lpddr4_odt_40 40 Ω
    lpddr4_odt_off Hi-Z
    (1) Model names based on IBIS file j7es_v0p2.ibs, DRA829 and TDA4VM IBIS File. While the IO model name should be the same across Jacinto 7 processors, the correct processor IBIS model must be used for simulations and can be obtained from the corresponding product home page.
    (2) Model names also used to represent the differential version of the model (models ending in _diff)