SPRUJ09D March   2022  – September 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 2.1 Sitara MCU+ Academy
    2. 2.2 If You Need Assistance
    3. 2.3 Important Usage Notes
  5. 2Control Card Overview
    1. 3.1 Kit Contents
    2. 3.2 Key Features
    3. 3.3 Component Identification
    4. 3.4 HSEC 180-pin Control Card Docking Station
    5. 3.5 Compliance
  6. 3Board Setup
    1. 4.1 Power Requirements
      1. 4.1.1 Power Input Using USB Type-C Connector
      2. 4.1.2 Power Status LEDs
      3. 4.1.3 Power Tree
      4. 4.1.4 Power Sequence
    2. 4.2 Push Buttons
    3. 4.3 Boot Mode Selection
    4. 4.4 JTAG Path Selection
  7. 4Hardware Description
    1. 5.1  Functional Block Diagram
    2. 5.2  GPIO Mapping
    3. 5.3  Reset
    4. 5.4  Clock
    5. 5.5  Memory Interface
      1. 5.5.1 QSPI
      2. 5.5.2 Board ID EEPROM
    6. 5.6  Ethernet Interface
      1. 5.6.1 RGMII
      2. 5.6.2 PRU-ICSS
      3. 5.6.3 LED Indication in RJ45 Connector
    7. 5.7  I2C
    8. 5.8  Industrial Application LEDs
    9. 5.9  SPI
    10. 5.10 UART
    11. 5.11 MCAN
    12. 5.12 FSI
    13. 5.13 JTAG
    14. 5.14 Test Automation Header
    15. 5.15 LIN
    16. 5.16 MMC
    17. 5.17 ADC and DAC
    18. 5.18 HSEC Pinout and Pinmux Mapping
  8. 5References
    1. 6.1 References
    2. 6.2 Other TI Components Used in This Design
  9.   Revision History
  10.   A E2 Design Changes
  11.   B E1 HSEC Pinout Table

4.3 Reset

Figure 4-2 shows the reset architecture of the AM263x Control Card.
GUID-20220419-SS0I-RVVB-HT0D-1KXHXBL8HRS4-low.png Figure 4-2 Reset Architecture

The AM263x SoC has the following resets:

  • PORz is the Power-On-Reset for the MAIN Domain.
  • WARMRESETn is the Warm Reset to MAIN Domain.

GUID-20220419-SS0I-RK8W-35TV-DMCFPFQ4VKPQ-low.png Figure 4-3 PORz Reset Signal Tree

The PORz signal is driven by a 3-input AND gate that generates a power on reset for the MAIN domain when:

  • The under voltage monitor (TPS3711DDCR) has an input voltage, VMAIN, that is below 4.48 V.
  • The 1.2-V buck converter (TPS62913RPUR) power good output is driven low by having an output voltage that is below the power-good threshold.
  • The user push button (SW2) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TA_PORZn) to a P-Channel MOSFET gate which causes V_GS of the PMOS to be less than zero and so the PORz signal connects to the PMOS drain which is tied directly to ground.

The PORz signal is tied to:

  • AM263x SoC PORz input
  • RGMII1 Ethernet PHY reset
  • ICSSM1 Gigabit Ethernet PHY reset
  • ICSSM2 Industrial Ethernet PHY reset
  • BOOTMODE buffer output enable

GUID-20220419-SS0I-1B9V-PSVC-LXLN1HZWPJ9R-low.png Figure 4-4 WARMRESETn Reset Signal Tree

The WARMRESETn signal creates a warm reset to the MAIN domain when:

  • The user push button (SW4) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TA_RESETz) to a P-Channel MOSFET gate which causes V_GS of the PMOS to be less than zero and so the RESETz signal connects to the PMOS drain which is tied directly to ground.

The WARMRESETn signal is tied to:

  • AM263x SoC WARMRESETN output
  • RESETz signal created from push button + PMOS logic
  • IO Expander reset
  • Micro SD reset

The AM263x Control Card also has an external interrupt to the SoC, INTn, that occurs when:

  • The user push button (SW1) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TA_GPIO1) to a P-Channel MOSFET gate which causes V_GS of the PMOS to be less than zero and so the INTn signal connects to the PMOS drain which is tied directly to ground.