SPRZ572 April   2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision 0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 0 Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8. 3.2.1 Advisory
      9.      Advisory
      10. 3.2.2 Advisory
      11.      Advisory
      12. 3.2.3 Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16. 3.2.4 Advisory
      17.      Advisory
      18. 3.2.5 Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
  6. 4Documentation Support
  7. 5Trademarks
  8. 6Revision History

1.2 Advisories Matrix

Table 1-2 Advisories Matrix
MODULE DESCRIPTION SILICON REVISIONS AFFECTED
0
ADC ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set Yes
ADC ADC: Degraded ADC Performance With ADCCLK Fractional Divider Yes
ADC ADC: Enable Power to All ADCs to Avoid Incorrect VREFHI/VREFLO Behavior Yes
ADC ADC: OSDETECT (Open/Shorts Detect) Logic Not Present Yes
ADC ADC: There is a Resistive Path Between the Shared Analog Inputs Present on the VREFHI/VREFLO Pins Yes
BOR BOR: VDDIO Between 2.45 V and 3.0 V can Result in Multiple XRSn Pulses Yes
CMPSS CMPSS: COMPxLATCH May Not Clear Properly Under Certain Conditions Yes
MCAN Message Order Inversion When Transmitting From Dedicated Tx Buffers Configured With Same Message ID Yes
ePWM ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the End of the Blanking Window Yes
ePWM ePWM: Trip Events Will Not be Filtered by the Blanking Window for the First 3 Cycles After the Start of a Blanking Window Yes
eQEP eQEP: Position Counter Incorrectly Reset on Direction Change During Index Yes
Flash Flash: Single-Bit ECC Error Interrupt is Not Generated Yes
FPU FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation Yes
GPIO GPIO: 5V Signal Cannot Drive Low When 20mA Drive Mode is Enabled for Select GPIOs Yes
GPIO GPIO: Open-Drain Configuration may Drive a Short High Pulse Yes
LIN LIN: Inconsistent Sync Field Error (ISFE) Flag/Interrupt Not Set When Sync Field is Erroneous Yes
MCD MCD: Missing Clock Detect Should be Disabled When the PLL is Enabled (PLLCLKEN = 1) Yes
Memory Memory: Prefetching Beyond Valid Memory Yes
Memory MPOST: Execution of Memory Power-On Self-Test will not Execute on Some Early Material Yes
SYSTEM SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a System Hang Yes
USB USB: USB DMA Event Triggers are not Supported Yes
Watchdog Watchdog: WDKEY Register is not EALLOW-Protected Yes