TIDUEY8 March 2023
Multichannel JESD204B designs need various clocks that are low-noise and high-frequency device clocks that are used to clock data converters, FPGA clocks, SYSREFs, and SYNC control signals for synchronizing multiple PLL synthesizer. In this design, the system clock device LMK04832-SP is used to generate the FPGA clocks, FPGA SYSREF signals, primary SYSREF signals for the data converters, and SYNC signals to multiple LMX2615-SP devices. Primary SYSREF signals are feeding to SYSREF_REQ inputs of the LMX2615-SP devices and act as primary SYSREF controlled through LMK04832-SP.
The LMK04832-SP is operating in PLL2 single-loop mode with 100-MHz input at OSCin and generates in-phase clocks out after internal SYNC and resetting the dividers. LMK04832-SP generates FPGA clocks at 160 MHz and SYSREF at 20-MHz frequencies using the internal VCO running at 3.2 GHz.