TIDUF06 August   2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 PCB and Form Factor
      2. 2.2.2 Power Supply Design
        1. 2.2.2.1 POC Filter
        2. 2.2.2.2 Power Supply Considerations
          1. 2.2.2.2.1 Choosing External Components
          2. 2.2.2.2.2 Choosing the Buck 1 Inductor
          3. 2.2.2.2.3 Choosing the Buck 2 and Buck 3 Inductors
          4. 2.2.2.2.4 Functional Safety
    3. 2.3 Highlighted Products
      1. 2.3.1 DS90UB953-Q1
      2. 2.3.2 TPS650330-Q1
      3. 2.3.3 IMX623
    4. 2.4 System Design Theory
  8. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Required Hardware
      1. 3.1.1 Hardware Setup
      2. 3.1.2 FPD-Link III I2C Initialization
      3. 3.1.3 IMX623 Initialization
    2. 3.2 Testing and Results
      1. 3.2.1 Test Setup
        1. 3.2.1.1 Power Supplies Startup
        2. 3.2.1.2 Power Supply Startup – 1.8 V Rail and Serializer PDB Setup
      2. 3.2.2 Test Results
        1. 3.2.2.1 Power Supplies Start Up
        2. 3.2.2.2 Power Supply Output Voltage Ripple
        3. 3.2.2.3 Power Supply Load Currents
        4. 3.2.2.4 I2C Communications
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 PMIC Layout Recommendations
      2. 4.3.2 PCB Layer Stackup
      3. 4.3.3 Serializer Layout Recommendations
      4. 4.3.4 Imager Layout Recommendations
      5. 4.3.5 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Related Documentation
  11. 6Trademarks

4.3.1 PMIC Layout Recommendations

The PMIC portion of the layout requires careful consideration to minimize both PCB area and noise. As EMI is a critical concern in automotive systems, the TPS650330-Q1 device includes a spread spectrum feature to reduce conducted and radiated emissions, allowing more flexibility with placement and layout for space-constrained applications. However, it is still recommended to follow as many best practices as possible. This includes minimizing the area traveled by switching currents between buck regulator input capacitor, inductor, and output capacitor with tight component placement and minimal return path to the PMIC thermal pad. Figure 4-1 shows an example of this for Buck 2.

GUID-9537D87A-49A0-4A43-B352-4E00A1E7FBC0-low.pngFigure 4-1 Buck 2 Layout Considerations

For the LDO, separation of input and output capacitor ground planes will reduce noise coupling from the switching rails to the sensitive analog rail. To further reduce noise coupling, the dedicated AGND pin of the PMIC is connected to the ground plane on an internal layer with a via, rather than directly to the noisier thermal pad on the top layer.