SNVS185F February   2002  – April 2017 LP3982

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 No-Load Stability
      2. 7.3.2 Fast Start-Up
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setting (ADJ Version Only)
        3. 8.2.2.3 Output Capacitance
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Noise Bypass Capacitor
        6. 8.2.2.6 Fault Detection
        7. 8.2.2.7 Power Dissipation
        8. 8.2.2.8 Estimating Junction Temperature
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 WSON Mounting
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 2.5-V to 6-V Input Range
  • MAX8860 Pin, Package, and Specification Compatible
  • 300-mA Output Current
  • 120-mV Typical Dropout at 300 mA
  • 90-μA Typical Quiescent Current
  • 1-nA Typical Shutdown Mode
  • 60-dB Typical PSRR
  • 120-μs Typical Turnon Time
  • Stable With Small Ceramic Output Capacitors
  • 37-μVRMS Output Voltage Noise
    (10 Hz to 100 kHz)
  • Overtemperature/Overcurrent Protection
  • ±2% Output Voltage Tolerance
  • Create a Custom Design Using the LP3982 With the WEBENCH® Power Designer

2 Applications

  • Wireless Handsets
  • DSP Core Power
  • Battery Powered Electronics
  • Portable Information Appliances

3 Description

The LP3982 low-dropout (LDO) CMOS linear regulator is available in 1.8-V, 2.5-V, 2.82-V, 3-V,
3.3-V, and adjustable versions. They deliver 300 mA of output current. Packaged in an 8-pin VSSOP, the LP3982 is pin- and package-compatible with Maxim's MAX8860. The LM3982 is also available in the small footprint WSON package.

The LP3982 suits battery-powered applications because of its shutdown mode (1 nA typical), low quiescent current (90 μA typical), and LDO voltage (120 mV typical). The low dropout voltage allows for more utilization of a battery’s available energy by operating closer to its end-of-life voltage. The LP3982 device's PMOS output transistor consumes relatively no drive current compared to PNP LDO regulators.

This PMOS regulator is stable with small ceramic capacitive loads (2.2 μF typical).

These devices also include regulation fault detection, a bandgap voltage reference, constant current limiting, and thermal-overload protection.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LP3982 WSON (8) 2.50 mm × 3.00 mm
VSSOP (8) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Application Circuit (Fixed VOUT Version)

LP3982 20036931.gif