SBAS654F June 2014  – March 2017 AMC1305L25 , AMC1305M05 , AMC1305M25

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configurations and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Power Ratings
    6. 7.6 Insulation Specifications
    7. 7.7 Safety-Related Certifications
    8. 7.8 Safety Limiting Values
    9. 7.9 Electrical Characteristics: AMC1305M05
    10. 7.10Electrical Characteristics: AMC1305x25
    11. 7.11Switching Characteristics
    12. 7.12Insulation Characteristics Curves
    13. 7.13Typical Characteristics
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Analog Input
      2. 8.3.2Modulator
      3. 8.3.3Digital Output
    4. 8.4Device Functional Modes
      1. 8.4.1Fail-Safe Output
      2. 8.4.2Output Behavior in Case of Full-Scale Input
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1Digital Filter Usage
    2. 9.2Typical Applications
      1. 9.2.1Frequency Inverter Application
        1. 9.2.1.1Design Requirements
        2. 9.2.1.2Detailed Design Procedure
        3. 9.2.1.3Application Curve
      2. 9.2.2Isolated Voltage Sensing
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2Detailed Design Procedure
        3. 9.2.2.3Application Curve
  10. 10Power-Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Examples
  12. 12Device and Documentation Support
    1. 12.1Documentation Support
      1. 12.1.1Related Documentation
    2. 12.2Related Links
    3. 12.3Receiving Notification of Documentation Updates
    4. 12.4Community Resource
    5. 12.5Trademarks
    6. 12.6Electrostatic Discharge Caution
    7. 12.7Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Specifications

Absolute Maximum Ratings

over the operating ambient temperature range (unless otherwise noted)(1)
MINMAXUNIT
Supply voltage, AVDD to AGND or DVDD to DGND–0.36.5V
Analog input voltage at AINP, AINN AGND – 6 AVDD + 0.5V
Digital input voltage at CLKIN, CLKIN_NDGND – 0.5DVDD + 0.5V
Input current to any pin except supply pins–1010mA
Maximum virtual junction temperature, TJ 150°C
Storage temperature, Tstg –65150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUEUNIT
V(ESD) Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
AVDD High-side (analog) supply voltage4.5 5.0 5.5 V
DVDDController-side (digital) supply voltage3.03.35.5V
TA Operating ambient temperature range–40 125 °C

Thermal Information

THERMAL METRIC(1) AMC1305xUNIT
DW (SOIC)
16 PINS
RθJA Junction-to-ambient thermal resistance 80.2°C/W
RθJC(top) Junction-to-case (top) thermal resistance 40.5°C/W
RθJB Junction-to-board thermal resistance 45.1°C/W
ψJT Junction-to-top characterization parameter 11.9°C/W
ψJB Junction-to-board characterization parameter 44.5°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Power Ratings

PARAMETERTEST CONDITIONSVALUEUNIT
PD Maximum power dissipation (both sides)AVDD = 5.5 V, DVDD = 5.5 V, LVDS, RLOAD = 100 Ω89.1mW
PD1 Maximum power dissipation (high-side supply)AVDD = 5.5 V45.1mW
PD2 Maximum power dissipation (low-side supply)DVDD = 5.5 V, LVDS, RLOAD = 100 Ω44mW

Insulation Specifications

PARAMETERTEST CONDITIONSVALUEUNIT
GENERAL
CLRMinimum air gap (clearance)(1)Shortest pin-to-pin distance through air≥ 8mm
CPGMinimum external tracking (creepage)(1)Shortest pin-to-pin distance across the package surface≥ 8mm
DTIDistance through insulationMinimum internal gap (internal clearance) of the double insulation (2 × 0.0135 mm)0.027mm
CTIComparative tracking indexDIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material groupAccording to IEC 60664-1I
Overvoltage category per IEC 60664-1Rated mains voltage ≤ 300 VRMSI-IV
Rated mains voltage ≤ 600 VRMSI-III
Rated mains voltage ≤ 1000 VRMSI-II
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12(2)
VIORM Maximum repetitive peak isolation voltageAt ac voltage (bipolar or unipolar)1414VPK
VIOWM Maximum-rated isolation working voltageAt ac voltage (sine wave)1000VRMS
At dc voltage1500VDC
VIOTM Maximum transient isolation voltageVTEST = VIOTM, t = 60 s (qualification test)7000VPK
VTEST = 1.2 x VIOTM, t = 1 s (100% production test)8400
VIOSM Maximum surge isolation voltage(3)Test method per IEC 60065, 1.2/50-μs waveform, VTEST = 1.6 x VIOSM = 10000 VPK (qualification)6250VPK
qpd Apparent charge(4)Method a, after input/output safety test subgroup 2 / 3, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 x VIORM = 1697 VPK, tm = 10 s≤ 5pC
Method a, after environmental tests subgroup 1, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 x VIORM = 2263 VPK, tm = 10 s≤ 5pC
Method b1, at routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 x VIORM = 2652 VPK, tm = 1 s≤ 5pC
CIO Barrier capacitance, input to output(5)VIO = 0.5 VPP at 1 MHz1.2 pF
RIO Insulation resistance, input to output(5)VIO = 500 V at TS = 150°C> 109 Ω
Pollution degree2
Climatic category40/125/21
UL1577
VISOWithstand isolation voltageVTEST = VISO = 5000 VRMS or 7000 VDC, t = 60 s (qualification test), VTEST = 1.2 x VISO = 6000 VRMS, t = 1 s (100% production test)5000VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves or ribs on the PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.

Safety-Related Certifications

VDEUL
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and DIN EN 60095 (VDE 0860): 2005-11Recognized under UL1577 component recognition and CSA component acceptance NO 5 programs
Reinforced insulationSingle protection
File number: 40040142 File number: E181974

Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A failure of the I/O circuitry may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
IS Safety input, output, or supply currentθJA = 80.2°C/W, AVDD = DVDD = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 3283 mA
θJA = 80.2°C/W, AVDD = DVDD = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 3432mA
PS Safety input, output, or total powerθJA = 80.2°C/W, TJ = 150°C, TA = 25°C, see Figure 41558(1)mW
TS Maximum safety temperature150°C
Input, output, or the sum of input and output power must not exceed this value.

The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

Electrical Characteristics: AMC1305M05

All minimum and maximum specifications at TA = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP = –50 mV to 50 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETERTEST CONDITIONSMINTYP MAXUNIT
ANALOG INPUTS
VClipping Maximum differential voltage input range
(AINP-AINN)
±62.5mV
FSRSpecified linear full-scale range
(AINP-AINN)
–5050mV
VCM Operating common-mode input range –0.032AVDD – 2V
CID Differential input capacitance2pF
IIB Input currentInputs shorted to AGND–97–72-57μA
RID Differential input resistance5
IOS Input offset current±5nA
CMTICommon-mode transient immunity15kV/μs
CMRRCommon-mode rejection ratiofIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max
–104dB
fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max
–75
BWInput bandwidth800kHz
DC ACCURACY
DNLDifferential nonlinearityResolution: 16 bits–0.990.99LSB
INLIntegral nonlinearity(3) Resolution: 16 bits–4±1.54LSB
EO Offset error Initial, at 25°C–50±2.550µV
TCEO Offset error thermal drift(1) –1.31.3μV/°C
EG Gain error Initial, at 25°C–0.3%–0.02%0.3%
TCEG Gain error thermal drift(2) –40±2040ppm/°C
PSRRPower-supply rejection ratioVAVDD from 4.5 to 5.5V, at dc105dB
AC ACCURACY
SNRSignal-to-noise ratiofIN = 1 kHz7681dB
SINADSignal-to-noise + distortionfIN = 1 kHz7681dB
THDTotal harmonic distortionfIN = 1 kHz–90–83dB
SFDRSpurious-free dynamic rangefIN = 1 kHz8392dB
DIGITAL INPUTS/OUTPUTS
External Clock
fCLKIN Input clock frequency52020.1MHz
DutyCLKIN Duty cycle5 MHz ≤ fCLKIN ≤ 20.1 MHz40%50%60%
CMOS Logic Family, CMOS with Schmitt-Trigger
IIN Input currentDGND ≤ VIN ≤ DVDD–11μA
CIN Input capacitance5 pF
VIH High-level input voltage0.7 × DVDDDVDD + 0.3 V
VIL Low-level input voltage–0.30.3 × DVDD V
CLOAD Output load capacitancefCLKIN = 20 MHz30pF
VOH High-level output voltageIOH = –20 µA DVDD – 0.1V
IOH = –4 mA DVDD – 0.4
VOL Low-level output voltageIOL = 20 µA 0.1V
IOL = 4 mA 0.4
POWER SUPPLY
AVDDHigh-side supply voltage4.55.05.5V
IAVDD High-side supply current6.58.2mA
PAVDD High-side power dissipation32.545.1mW
DVDDController-side supply voltage3.03.35.5V
IDVDD Controller-side supply current3.0 V ≤ DVDD ≤ 3.6 V2.74.0mA
4.5 V ≤ DVDD ≤ 5.5 V3.25.5
PDVDD Controller-side power dissipation3.0 V ≤ DVDD ≤ 3.6 V8.914.4mW
4.5 V ≤ DVDD ≤ 5.5 V16.030.3
Offset error drift is calculated using the box method as described by the following equation: AMC1305L25 AMC1305M05 AMC1305M25 ec_eodrift_bas654.gif
Gain error drift is calculated using the box method as described by the following equation: AMC1305L25 AMC1305M05 AMC1305M25 ec_egdrift_bas654.gif
Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

Electrical Characteristics: AMC1305x25

All minimum and maximum specifications at TA = –40°C to 125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP = –250 mV to 250 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETERTEST CONDITIONSMINTYP MAXUNIT
ANALOG INPUTS
VClipping Maximum differential voltage input range
(AINP-AINN)
±312.5mV
FSRSpecified linear full-scale range
(AINP-AINN)
–250 250mV
VCM Operating common-mode input range   –0.16 AVDD – 2V
CID Differential input capacitance 1 pF
IIB Input currentInputs shorted to AGND–82 –60–48μA
RID Differential input resistance 25
IOS Input offset current ±5 nA
CMTICommon-mode transient immunity 15 kV/μs
CMRRCommon-mode rejection ratiofIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max
–95 dB
fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max
–76
BWInput bandwidth 1000 kHz
DC ACCURACY
DNLDifferential nonlinearityResolution: 16 bits–0.99 0.99LSB
INLIntegral nonlinearity(1) Resolution: 16 bits–4 ±1.54LSB
EO Offset error Initial, at 25°C–150 ±40150µV
TCEO Offset error thermal drift(2) –1.3 1.3μV/°C
EG Gain error Initial, at 25°C–0.3 –0.020.3%FS
TCEG Gain error thermal drift(3) –40±2040ppm/°C
PSRRPower-supply rejection ratioVAVDD from 4.5 V to 5.5 V, at dc 90 dB
AC ACCURACY
SNRSignal-to-noise ratiofIN = 1 kHz82 85 dB
SINADSignal-to-noise + distortionfIN = 1 kHz80 84 dB
THDTotal harmonic distortionfIN = 1 kHz –90–83dB
SFDRSpurious-free dynamic rangefIN = 1 kHz83 92 dB
DIGITAL INPUTS/OUTPUTS
External Clock
fCLKIN Input clock frequency 52020.1MHz
DutyCLKIN Duty cycle5 MHz ≤ fCLKIN ≤ 20.1 MHz40%50%60%
CMOS Logic Family (AMC1305M25), CMOS with Schmitt-Trigger
IIN Input currentDGND ≤ VIN ≤ DVDD–1 1μA
CIN  Input capacitance 5 pF
VIH High-level input voltage 0.7 × DVDD DVDD + 0.3 V
VIL  Low-level input voltage –0.3 0.3 × DVDD V
CLOAD Output load capacitancefCLKIN = 20 MHz 30 pF
VOH High-level output voltageIOH = –20 µA DVDD – 0.1 V
IOH = –4 mA DVDD – 0.4
VOL Low-level output voltageIOL = 20 µA 0.1V
IOL = 4 mA 0.4
LVDS Logic Family (AMC1305L25)
VOD Differential output voltageRLOAD = 100 Ω250350450mV
VOCM Output common-mode voltage 1.1251.231.375V
IS Output short-circuit current 24mA
VICM Input common-mode voltageVID = 100 mV0.05 1.253.25V
VID Differential input voltage 100 350600mV
IIN Input currentDGND ≤ VIN ≤ 3.3 V–24020µA
POWER SUPPLY
AVDDHigh-side supply voltage 4.55.05.5V
IAVDD High-side supply current 6.58.2mA
PAVDD High-side power dissipation 32.545.1mW
DVDDController-side supply voltage 3.03.35.5V
IDVDD Controller-side supply currentAMC1305L25, RLOAD = 100 Ω6.18.0mA
AMC1305M25, 3.0 ≤ DVDD ≤ 3.6 V,
CLOAD = 5 pF
2.74.0
AMC1305M25, 4.5 ≤ DVDD ≤ 5.5 V,
CLOAD = 5 pF
3.25.5
PDVDD Controller-side power dissipationAMC1305L25, RLOAD = 100 Ω20.144.0mW
AMC1305M25, 3.0 ≤ DVDD ≤ 3.6 V,
CLOAD = 5 pF
8.914.4
AMC1305M25, 4.5 ≤ DVDD ≤ 5.5 V,
CLOAD = 5 pF
16.030.3
Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as the number of LSBs or as a percent of the specified linear full-scale range FSR.
Offset error drift is calculated using the box method as described by the following equation: AMC1305L25 AMC1305M05 AMC1305M25 ec_eodrift_bas654.gif
Gain error drift is calculated using the box method as described by the following equation: AMC1305L25 AMC1305M05 AMC1305M25 ec_egdrift_bas654.gif

Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERMINTYPMAXUNIT
tCLK CLKIN, CLKIN_N clock period 49.75 50 200 ns
tHIGH CLKIN, CLKIN_N clock high time19.9 25120 ns
tLOW CLKIN, CLKIN_N clock low time19.925120ns
tD Falling edge of CLKIN, CLKIN_N to DOUT, DOUT_N valid delay,
CLOAD = 5 pF
015ns
tISTART Interface startup time
(DVDD at 3.0 V min to DOUT, DOUT_N valid with AVDD ≥ 4.5 V)
3232CLKIN cycles
tASTART Analog startup time (AVDD step up to 4.5 V with DVDD ≥ 3.0 V)1ms
AMC1305L25 AMC1305M05 AMC1305M25 tim_int_bas654.gif Figure 1. Digital Interface Timing
AMC1305L25 AMC1305M05 AMC1305M25 tim_start_bas654.gif Figure 2. Digital Interface Startup Timing

Insulation Characteristics Curves

AMC1305L25 AMC1305M05 AMC1305M25 D043_SBAS654.gif
Figure 3. Thermal Derating Curve for Safety Limiting Current per VDE
AMC1305L25 AMC1305M05 AMC1305M25 Figure 3.gif
TA up to 150°C, stress voltage frequency = 60 Hz
Figure 5. Reinforced Isolation Capacitor Lifetime Projection
AMC1305L25 AMC1305M05 AMC1305M25 D044_SBAS655.gif
Figure 4. Thermal Derating Curve for Safety Limiting Power per VDE

Typical Characteristics

At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, unless otherwise noted.
AMC1305L25 AMC1305M05 AMC1305M25 D001_SBAS654.gif
Figure 6. Input Current vs Input Common-Mode Voltage
AMC1305L25 AMC1305M05 AMC1305M25 D003_SBAS654.gif
Figure 8. Integral Nonlinearity vs Input Signal Amplitude
AMC1305L25 AMC1305M05 AMC1305M25 D005_SBAS654.gif
AMC1305x25
Figure 10. Offset Error vs High-Side Supply Voltage
AMC1305L25 AMC1305M05 AMC1305M25 D007_SBAS654.gif
AMC1305x25
Figure 12. Offset Error vs Temperature
AMC1305L25 AMC1305M05 AMC1305M25 D009_SBAS654.gif
Figure 14. Offset Error vs Clock Frequency
AMC1305L25 AMC1305M05 AMC1305M25 D011_SBAS654.gif
Figure 16. Gain Error vs Temperature
AMC1305L25 AMC1305M05 AMC1305M25 D013_SBAS654.gif
Figure 18. Power-Supply Rejection Ratio vs
Ripple Frequency
AMC1305L25 AMC1305M05 AMC1305M25 D015_SBAS654.gif
Figure 20. SNR and SINAD vs Temperature
AMC1305L25 AMC1305M05 AMC1305M25 D017_SBAS654.gif
Figure 22. SNR and SINAD vs Input Signal Frequency
AMC1305L25 AMC1305M05 AMC1305M25 D019_SBAS654.gif
AMC1305M05
Figure 24. SNR and SINAD vs Input Signal Amplitude
AMC1305L25 AMC1305M05 AMC1305M25 D021_SBAS654.gif
Figure 26. Total Harmonic Distortion vs Temperature
AMC1305L25 AMC1305M05 AMC1305M25 D023_SBAS654.gif
Figure 28. Total Harmonic Distortion vs
Input Signal Frequency
AMC1305L25 AMC1305M05 AMC1305M25 D025_SBAS654.gif
AMC1305M05
Figure 30. Total Harmonic Distortion vs
Input Signal Amplitude
AMC1305L25 AMC1305M05 AMC1305M25 D027_SBAS654.gif
Figure 32. Spurious-Free Dynamic Range vs Temperature
AMC1305L25 AMC1305M05 AMC1305M25 D029_SBAS654.gif
Figure 34. Spurious-Free Dynamic Range vs
Input Signal Frequency
AMC1305L25 AMC1305M05 AMC1305M25 D031_SBAS654.gif
AMC1305M05
Figure 36. Spurious-Free Dynamic Range vs
Input Signal Amplitude
AMC1305L25 AMC1305M05 AMC1305M25 D033_SBAS654.gif
AMC1305x25, 4096-point FFT, VIN = 500 mVPP
Figure 38. Frequency Spectrum with 5-kHz Input Signal
AMC1305L25 AMC1305M05 AMC1305M25 D035_SBAS654.gif
AMC1305M05, 4096-point FFT, VIN = 500 mVPP
Figure 40. Frequency Spectrum with 5-kHz Input Signal
AMC1305L25 AMC1305M05 AMC1305M25 D037_SBAS654.gif
Figure 42. High-Side Supply Current vs Temperature
AMC1305L25 AMC1305M05 AMC1305M25 D039_SBAS654.gif
Figure 44. Controller-Side Supply Current vs
Controller-Side Supply Voltage (3.3 V, nom)
AMC1305L25 AMC1305M05 AMC1305M25 D041_SBAS654.gif
Figure 46. Controller-Side Supply Current vs Temperature
AMC1305L25 AMC1305M05 AMC1305M25 D002_SBAS654.gif
Figure 7. Common-Mode Rejection Ratio vs
Input Signal Frequency
AMC1305L25 AMC1305M05 AMC1305M25 D004_SBAS654.gif
Figure 9. Integral Nonlinearity vs Temperature
AMC1305L25 AMC1305M05 AMC1305M25 D006_SBAS654.gif
AMC1305M05
Figure 11. Offset Error vs High-Side Supply Voltage
AMC1305L25 AMC1305M05 AMC1305M25 D008_SBAS654.gif
AMC1305M05
Figure 13. Offset Error vs Temperature
AMC1305L25 AMC1305M05 AMC1305M25 D010_SBAS654.gif
Figure 15. Gain Error vs High-Side Supply Voltage
AMC1305L25 AMC1305M05 AMC1305M25 D012_SBAS654.gif
Figure 17. Gain Error vs Clock Frequency
AMC1305L25 AMC1305M05 AMC1305M25 D014_SBAS654.gif
Figure 19. SNR and SINAD vs High-Side Supply Voltage
AMC1305L25 AMC1305M05 AMC1305M25 D016_SBAS654.gif
Figure 21. SNR and SINAD vs Clock Frequency
AMC1305L25 AMC1305M05 AMC1305M25 D018_SBAS654.gif
AMC1305x25
Figure 23. SNR and SINAD vs Input Signal Amplitude
AMC1305L25 AMC1305M05 AMC1305M25 D020_SBAS654.gif
Figure 25. Total Harmonic Distortion vs
High-Side Supply Voltage
AMC1305L25 AMC1305M05 AMC1305M25 D022_SBAS654.gif
Figure 27. Total Harmonic Distortion vs Clock Frequency
AMC1305L25 AMC1305M05 AMC1305M25 D024_SBAS654.gif
AMC1305x25
Figure 29. Total Harmonic Distortion vs
Input Signal Amplitude
AMC1305L25 AMC1305M05 AMC1305M25 D026_SBAS654.gif
Figure 31. Spurious-Free Dynamic Range vs
High-Side Supply Voltage
AMC1305L25 AMC1305M05 AMC1305M25 D028_SBAS654.gif
Figure 33. Spurious-Free Dynamic Range vs
Clock Frequency
AMC1305L25 AMC1305M05 AMC1305M25 D030_SBAS654.gif
AMC1305x25
Figure 35. Spurious-Free Dynamic Range vs
Input Signal Amplitude
AMC1305L25 AMC1305M05 AMC1305M25 D032_SBAS654.gif
AMC1305x25, 4096-point FFT, VIN = 500 mVPP
Figure 37. Frequency Spectrum with 1-kHz Input Signal
AMC1305L25 AMC1305M05 AMC1305M25 D034_SBAS654.gif
AMC1305M05, 4096-point FFT, VIN = 500 mVPP
Figure 39. Frequency Spectrum with 1-kHz Input Signal
AMC1305L25 AMC1305M05 AMC1305M25 D036_SBAS654.gif
Figure 41. High-Side Supply Current vs
High-Side Supply Voltage
AMC1305L25 AMC1305M05 AMC1305M25 D038_SBAS654.gif
Figure 43. High-Side Supply Current vs Clock Frequency
AMC1305L25 AMC1305M05 AMC1305M25 D040_SBAS654.gif
Figure 45. Controller-Side Supply Current vs
Controller-Side Supply Voltage (5 V, nom)
AMC1305L25 AMC1305M05 AMC1305M25 D042_SBAS654.gif
Figure 47. Controller-Side Supply Current vs
Clock Frequency