SLASEM6A October 2017  – December 2017 TAS2770


  1. 1     Features
  2. 2     Applications
  3. 3     Description
  4. DeviceImages
    1. FunctionalBlock Diagram
  5. 4     Revision History
  6. 5     Pin Configuration and Functions
    1. PinFunctions
  7. 6     Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6I2C Timing Requirements
    7. 6.7TDM Port Timing Requirements
    8. 6.8PDM Port Timing Requirements
    9. 6.9Typical Characteristics
  8. 7     Parameter Measurement Information
  9. 8     Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Device Mode and Address Selection
      2. 8.3.2General I2C Operation
      3. 8.3.3Single-Byte and Multiple-Byte Transfers
      4. 8.3.4Single-Byte Write
      5. 8.3.5Multiple-Byte Write and Incremental Multiple-Byte Write
      6. 8.3.6Single-Byte Read
      7. 8.3.7Multiple-Byte Read
      8. 8.3.8Register Organization
    4. 8.4Device Functional Modes
      1. 8.4.1PDM Input
      2. 8.4.2TDM Port
      3. 8.4.3Playback Signal Path
        1. Pass Filter
        2. Volume Control and Amplifier Output Level
        3. Audio Playback Selection
        4. Tracking Limiter with Brown Out Prevention
        5. Chip Limiter Alignment
          1. Mode
        6. Settings
      4. 8.4.4 SAR ADC
      5. 8.4.5IV Sense
      6. 8.4.6Clocks and PLL
    5. 8.5Operational Modes
      1. 8.5.1Hardware Shutdown
      2. 8.5.2Software Shutdown
      3. 8.5.3Mute
      4. 8.5.4Active
      5. 8.5.5Mode Control and Software Reset
    6. 8.6Faults and Status
    7. 8.7Power Sequencing Requirements
    8. 8.8Digital Input Pull Downs
    9. 8.9Register Maps
      1. 8.9.1Register Summary Table Book=0x00 Page=0x00
      2. 8.9.2Register Maps
        1. PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
          1. Table82. Device Page Field Descriptions
        2. SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
          1. Table83. Software Reset Field Descriptions
        3. PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
          1. Table84. Power Control Field Descriptions
        4. PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
          1. Table85. Playback Configuration 0 Field Descriptions
        5. PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
          1. Table86. Playback Configuration 1 Field Descriptions
        6. PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
          1. Table87. Playback Configuration 2 Field Descriptions
        7. PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
          1. Table88. Playback Configuration 3 Field Descriptions
        8. MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
          1. Table89. Misc Configuration Field Descriptions
        9. PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
          1. Table90. PDM Input Register 0 Field Descriptions
        10. (book=0x00 page=0x00 address=0x09) [reset=8h]
          1. Table91. PDM Configuration 1 Field Descriptions
        11. (book=0x00 page=0x00 address=0x0A) [reset=7h]
          1. Table92. TDM Configuration 0 Field Descriptions
        12. (book=0x00 page=0x00 address=0x0B) [reset=2h]
          1. Table93. TDM Configuration 1 Field Descriptions
        13. (book=0x00 page=0x00 address=0x0C) [reset=Ah]
          1. Table94. TDM Configuration 2 Field Descriptions
        14. (book=0x00 page=0x00 address=0x0D) [reset=10h]
          1. Table95. TDM Configuration 3 Field Descriptions
        15. (book=0x00 page=0x00 address=0x0E) [reset=13h]
          1. Table96. TDM Configuration 4 Field Descriptions
        16. (book=0x00 page=0x00 address=0x0F) [reset=2h]
          1. Table97. TDM Configuration 5 Field Descriptions
        17. (book=0x00 page=0x00 address=0x10) [reset=0h]
          1. Table98. TDM Configuration 6 Field Descriptions
        18. (book=0x00 page=0x00 address=0x11) [reset=4h]
          1. Table99. TDM Configuration 7 Field Descriptions
        19. (book=0x00 page=0x00 address=0x12) [reset=6h]
          1. Table100. TDM Configuration 8 Field Descriptions
        20. (book=0x00 page=0x00 address=0x13) [reset=7h]
          1. Table101. TDM Configuration 9 Field Descriptions
        21. (book=0x00 page=0x00 address=0x14) [reset=8h]
          1. Table102. TDM Configuration 10 Field Descriptions
        22. (book=0x00 page=0x00 address=0x15) [reset=14h]
          1. Table103. Limiter Configuration 0 Field Descriptions
        23. (book=0x00 page=0x00 address=0x16) [reset=76h]
          1. Table104. Limiter Configuration 1 Field Descriptions
        24. (book=0x00 page=0x00 address=0x17) [reset=10h]
          1. Table105. Limiter Configuration 2 Field Descriptions
        25. (book=0x00 page=0x00 address=0x18) [reset=6Eh]
          1. Table106. Limiter Configuration 3 Field Descriptions
        26. (book=0x00 page=0x00 address=0x19) [reset=1Eh]
          1. Table107. Limiter Configuration 4 Field Descriptions
        27. (book=0x00 page=0x00 address=0x1A) [reset=58h]
          1. Table108. Limiter Configuration 5 Field Descriptions
        28. (book=0x00 page=0x00 address=0x1B) [reset=1h]
          1. Table109. Brown Out Prevention 0 Field Descriptions
        29. (book=0x00 page=0x00 address=0x1C) [reset=14h]
          1. Table110. Brown Out Prevention 1 Field Descriptions
        30. (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
          1. Table111. Brown Out Prevention 2 Field Descriptions
        31. (book=0x00 page=0x00 address=0x1E) [reset=0h]
          1. Table112. Inter Chip Limiter Alignment 0 Field Descriptions
        32. (book=0x00 page=0x00 address=0x1F) [reset=0h]
          1. Table113. Inter Chip Limiter Alignment 1 Field Descriptions
        33. (book=0x00 page=0x00 address=0x20) [reset=FCh]
          1. Table114. Interrupt Mask 0 Field Descriptions
        34. (book=0x00 page=0x00 address=0x21) [reset=B1h]
          1. Table115. Interrupt Mask 1 Field Descriptions
        35. (book=0x00 page=0x00 address=0x22) [reset=0h]
          1. Table116. Live Interrupt Readback 0 Field Descriptions
        36. (book=0x00 page=0x00 address=0x23) [reset=0h]
          1. Table117. Live Interrupt Readback 1 Field Descriptions
        37. (book=0x00 page=0x00 address=0x24) [reset=0h]
          1. Table118. Latched Interrupt Readback 0 Field Descriptions
        38. (book=0x00 page=0x00 address=0x25) [reset=0h]
          1. Table119. Latched Interrupt Readback 1 Field Descriptions
        39. (book=0x00 page=0x00 address=0x26) [reset=0h]
          1. Table1. INT_LTCH2 Register Address: 0x26
          2. Table120. INT_LTCH2 Field Descriptions
        40. (book=0x00 page=0x00 address=0x27) [reset=0h]
          1. Table121. SAR ADC Conversion 0 Field Descriptions
        41. (book=0x00 page=0x00 address=0x28) [reset=0h]
          1. Table122. SAR ADC Conversion 1 Field Descriptions
        42. (book=0x00 page=0x00 address=0x29) [reset=0h]
          1. Table123. SAR ADC Conversion 2 Field Descriptions
        43. (book=0x00 page=0x00 address=0x2A) [reset=0h]
          1. Table124. SAR ADC Conversion 2 Field Descriptions
        44. (book=0x00 page=0x00 address=0x30) [reset=5h]
          1. Table125. Interrupt Configuration Field Descriptions
        45. (book=0x00 page=0x00 address=0x31) [reset=0h]
          1. Table126. Digital Input Pin Pull Down Field Descriptions
        46. (book=0x00 page=0x00 address=0x32) [reset=81h]
          1. Table127. Misc Configuration Field Descriptions
        47. (book=0x00 page=0x00 address=0x3C) [reset=Dh]
          1. Table128. Clock Configuration Field Descriptions
        48. (book=0x00 page=0x00 address=0x77) [reset=7Fh]
          1. Table129. TDM Clock detection monitor Field Descriptions
        49. (book=0x00 page=0x00 address=0x7D) [reset=20h]
          1. Table130. Revision and PG ID Field Descriptions
        50. (book=0x00 page=0x00 address=0x7E) [reset=0h]
          1. Table131. I2C Checksum Field Descriptions
        51. (book=0x00 page=0x00 address=0x7F) [reset=0h]
          1. Table132. Device Book Field Descriptions
  10. 9     Application and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
        2. Input Capacitance
        3. Decoupling Capacitors
        4. Bootstrap Capacitors
      3. 9.2.3Application Curves
    3. 9.3Initialization Set Up
      1. 9.3.1Initial Device Configuration - Auto Rate
      2. 9.3.2Initial Device Configuration - 48 kHz
      3. 9.3.3Initial Device Configuration - 44.1 kHz
      4. 9.3.4Sample Rate Change - 48 kHz to 44.1kHz
      5. 9.3.5Sample Rate Change - 44.1 kHz to 48 kHz
      6. 9.3.6Device Mute
      7. 9.3.7Device Un-Mute
      8. 9.3.8Device Sleep
      9. 9.3.9Device Wake
  11. 10    Power Supply Recommendations
  12. 11    Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  13. 12    Device and Documentation Support
    1. 12.1Receiving Notification of Documentation Updates
    2. 12.2Community Resources
    3. 12.3Trademarks
    4. 12.4Electrostatic Discharge Caution
    5. 12.5Glossary
  14. 13    Mechanical, Packaging, and Orderable Information
    1. 13.1Package Option Addendum
      1. 13.1.1Packaging Information
      2. 13.1.2Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFF|30
  • RJQ|26
Orderable Information

PDM Input

The TAS2770 provides one PDM input that can be used for low latency audio playback or sensor aggregation in TDM/I2C mode. Figure 42 below illustrates the double data rate nature of the PDM inputs. Each input has two interleaved PDM channels, one sampled by the rising edge and the other by the falling edge of the clock.

TAS2770 tas5770l_pdm_func.gifFigure 42. PDM Waveform

The PDM inputs are sampled by the PDMCK pin, which can be independently configured as either a PDM clock slave input or a PDM clock master output. The PDM_EDGE[1:0] and PDM_SLV[1:0] register bits select the sample clock edge and master/slave mode for each of the two PDM inputs. In master mode the PDMCK pin can disable the clocks (and drive a logic 0) by setting the PDM_GATE[1:0] register bits low. The PDM_CLK[1:0] register bits select which clock is used to sample each PDM input.

TAS2770 tas5770l_pdm_block_diagram.gifFigure 43. PDM Data and Clock Input Block Diagram

When configured as a clock slave, the PDM clock input does not require a specific phase relationship to the system clock (SBCLK in TDM/I2C Mode), but must have an exact frequency relationship to the audio sample rate. This is equivalent to 64/32/16 (~3 MHz) or 128/64/32 (~6 MHz) times a single/double/quadruple speed sample rate. The PDM rate is set by the PDM_RATE1[1:0] register bits.

When the PDMCK pin is configured as a clock master, the TAS2770 will output a 50% duty cycle clock of frequency that is set by the PDM_RATE1[1:0] register bits (64/32/16 or 128/64/32 times a single/double/quadruple speed sample rate).

The PDM_MAP register bit selects which PDM pin is used for audio playback input and which is used for PDM sensor input. The PDM sensor input can be decimated (time aligned with the IV sense) and transmitted on the SDOUT pin when the device is in TDM/I2C mode.

Table 2. PDM Input Capture Edge

PDM Input PinRegister BitValueCapture Edge
PDMDPDM_EDGE[1]0Rising (default)

Table 3. PDM Clock Slave

PDM Input PinRegister BitValueMaster/Slave
PDMDPDM_SLV[1]0Slave (default)

Table 4. PDM Clock Select

PDM Input PinRegister BitValueClock Source
1PDMCK (default)

Table 5. PDM Master Mode Clock Gate

PDM Clock PinRegister BitValueGating
PDMCKPDM_GATE[1]0Gated Off (default)

Table 6. PDM Input Sample Rate

PDM Input PinRegister BitsValueSample Rate
PDMDPDM_RATE1[1:0]002.54 - 3.38 MHz (default)
015.08 - 6.76 MHz

Table 7. PDM Pin Mapping

0PDMD pin for sensor input (default)
1PDMD pin for playback