SLLSE32G November   2010  – November 2017 TUSB1310A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
    2. 3.2 Configuration Pins
    3. 3.3 Signal Descriptions
      1. 3.3.1 PIPE
      2. 3.3.2 ULPI
      3. 3.3.3 Clocking
      4. 3.3.4 JTAG Interface
      5. 3.3.5 Reset and Output Control Interface
      6. 3.3.6 Strap Options
      7. 3.3.7 USB Interfaces
      8. 3.3.8 Special Connect
      9. 3.3.9 Power and Ground
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Device Power-Consumption Summary
    5. 4.5 DC Characteristics for 1.8-V Digital I/O
    6. 4.6 Thermal Characteristics
    7. 4.7 Timing Characteristics
      1. 4.7.1 Power-Up and Reset Timing
      2. 4.7.2 PIPE Transmit
      3. 4.7.3 PIPE Receive
      4. 4.7.4 ULPI Parameters
      5. 4.7.5 ULPI Clock
      6. 4.7.6 ULPI Transmit
      7. 4.7.7 ULPI Receive Timing
    8. 4.8 Typical Characteristics
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Power On and Reset
        1. 5.3.1.1 RESETN and PHY_RESETN: Hardware Reset
        2. 5.3.1.2 ULPI Reset: Software Reset
        3. 5.3.1.3 OUT_ENABLE: Output Enable
        4. 5.3.1.4 Power-Up Sequence
      2. 5.3.2 Clocks
        1. 5.3.2.1 Clock Distribution
        2. 5.3.2.2 Output Clock
      3. 5.3.3 Power State Transition Time
      4. 5.3.4 Power Management
        1. 5.3.4.1 USB Power Management
      5. 5.3.5 Receiver Status
        1. 5.3.5.1 Clock Tolerance Compensation
        2. 5.3.5.2 Receiver Detection
        3. 5.3.5.3 8b/10b Decode Errors
        4. 5.3.5.4 Elastic Buffer Errors
        5. 5.3.5.5 Disparity Errors
      6. 5.3.6 Loopback
      7. 5.3.7 Adaptive Equalizer
    4. 5.4 Device Functional Modes
      1. 5.4.1 USB 3.0 Mode
      2. 5.4.2 USB 2.0 Mode
      3. 5.4.3 ULPI Modes
    5. 5.5 Register Maps
      1. 5.5.1  Vendor ID and Product ID (00h-03h)
      2. 5.5.2  Function Control (04h-06h)
      3. 5.5.3  Interface Control (07h-09h)
      4. 5.5.4  OTG Control
      5. 5.5.5  USB Interrupt Enable Rising (0Dh-0Fh)
      6. 5.5.6  USB Interrupt Enable Falling (10h-12h)
      7. 5.5.7  USB Interrupt Status (13h)
      8. 5.5.8  USB Interrupt Latch (14h)
      9. 5.5.9  Debug (15h)
      10. 5.5.10 Scratch Register (16-18h)
  6. 6Application, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
        1. 6.2.1.1 Clock Source Requirements
          1. 6.2.1.1.1 Clock Source Selection Guide
          2. 6.2.1.1.2 Oscillator
          3. 6.2.1.1.3 Crystal
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Chip Connection on PCB
          1. 6.2.2.1.1 USB Connector Pins Connection
          2. 6.2.2.1.2 Clock Connections
      3. 6.2.3 Application Curve
      4. 6.2.4 Layout
        1. 6.2.4.1 Layout Guidelines
          1. 6.2.4.1.1 High-Speed Differential Routing
          2. 6.2.4.1.2 SuperSpeed Differential Routing
        2. 6.2.4.2 Layout Example
    3. 6.3 Power Supply Recommendations
      1. 6.3.1 1.1-V and 1.8-V Digital Supply
      2. 6.3.2 1.1-V, 1.8-V and 3.3-V Analog Supplies
      3. 6.3.3 Capacitor Selection Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
      2. 7.1.2 Community Resources
    2. 7.2 Trademarks
    3. 7.3 Electrostatic Discharge Caution
    4. 7.4 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Pin Configuration and Functions

Figure 3-1 shows the 175-pin ZAY plastic ball grid array (NFBGA) pin assignments.

Figure 3-1 175-Pin ZAY NFBGA (Top View)

3.1 Pin Attributes

Table 3-1 Pin Types

TYPE DESCRIPTION
I Input
O Output
I/O Input/output
PD, PU Internal pullup, internal pulldown
S Strapping pin
P Power supply
G Ground

3.2 Configuration Pins

The configuration pins are not latched by RESETN.

Table 3-2 Configuration Pins

SIGNAL NAME TYPE PIN NO. MODE NAME DESCRIPTION
PHY_MODE1 I, PD H12 USB Must be set to 0. Operates as USB 3.0 transceiver.
PHY_MODE0 I, PU J12 USB Must be set to 1. Operates as USB 3.0 transceiver.

3.3 Signal Descriptions

3.3.1 PIPE

The TUSB1310A supports 16-bit SDR mode with a 250-MHz clock.

Table 3-3 PIPE Signal Descriptions

SIGNAL NAME TYPE BALL NO. DESCRIPTION
TX_CLK I K1 TX_DATA and TX_DATAK clock for source synchronous PIPE. This clock frequency is the same as PCLK frequency. The rising edge of the clock is the reference for all signals.
TX_DATA15 I G2 Parallel USB SuperSpeed data input bus.
The 16 bits represent 2 symbols of transmit data where TX_DATA7-0 is the first symbol to be transmitted, and TX_DATA15-8 is the second symbol.
TX_DATA14 H2
TX_DATA13 H1
TX_DATA12 J2
TX_DATA11 L3
TX_DATA10 L2
TX_DATA9 M2
TX_DATA8 M1
TX_DATA7 N1
TX_DATA6 P1
TX_DATA5 N2
TX_DATA4 P2
TX_DATA3 N3
TX_DATA2 P3
TX_DATA1 N4
TX_DATA0 P5
TX_DATAK1 I G1 Data/Control for the symbols of transmit data. TX_DATAK0 corresponds to the low-byte of TX_DATA, TX_DATAK1 to the upper byte.
TX_DATAK0 J1
PCLK O A6 Parallel interface data clock. All data movement across the parallel PIPE is synchronous to this clock. This clock operates at 250 MHz. The rising edge of the clock is the reference for all signals.
RX_DATA15 O B9 Parallel USB SuperSpeed data output bus.
The 16 bits represent 2 symbols of receive data where RX_DATA7-0 is the first symbol received, and RX_DATA15-8 is the second.
RX_DATA14 A9
RX_DATA13 A8
RX_DATA12 B8
RX_DATA11 B5
RX_DATA10 B4
RX_DATA9 A4
RX_DATA8 B3
RX_DATA7 A3
RX_DATA6 A2
RX_DATA5 B1
RX_DATA4 C2
RX_DATA3 C1
RX_DATA2 D1
RX_DATA1 D2
RX_DATA0 E2
RX_DATAK1 O B7 Data/Control for the symbols of receive data. RX_DATAK0 corresponds to the low-byte of RX_DATA, RX_DATAK1 to the upper byte. A value of zero indicates a data byte; a value of 1 indicates a control byte.
RX_DATAK0 A7
RX_VALID O F1 Active High. Indicates symbol lock and valid data on RX_DATA and RX_DATAK.
CONTROL AND STATUS SIGNALS
PHY_RESETN I, PU J3 Active Low. Resets the transmitter and receiver. This signal is asynchronous.
TX_DETRX_LPBK I, PD M6 Active High. Used to tell the PHY to begin a receiver detection operation or to begin loopback.
TX_ELECIDLE I K3 Active High. Forces TX output to electrical idle depending on the power state.
RX_ELECIDLE S, I/O, PD F3 Active High. While deasserted with the PHY in P0, P1, P2, or P3, indicates detection of LFPS.
RX_STATUS2 O C7 Encodes receiver status and error codes for the received data stream when receiving data.
RX_STATUS1 C6 BIT 2 BIT 1 BIT 0 DESCRIPTION
RX_STATUS0 C5 0 0 0 Received data OK
0 0 1 1 SKP ordered set added
0 1 0 1 SKP ordered set removed
0 1 1 Receiver detected
1 0 0 8B/10B decode error
1 0 1 Elastic buffer overflow
1 1 0 Elastic buffer underflow.
This error code is not used if the elasticity buffer is operating in the nominal buffer empty mode.
1 1 1 Receive disparity error
POWER_DOWN1 I G3 Power up and down the transceiver power states.
POWER_DOWN0 H3 BIT 1 BIT 0 DESCRIPTION
0 0 P0, normal operation
0 1 P1, low recovery time latency, power saving state
1 0 P2, longer recovery time latency, low-power state
1 1 P3, lowest power state
When transitioning from P3 to P0, the signaling is asynchronous.
PHY_STATUS S, I/O, PD E3 Active High. Used to communicate completion of several PHY functions including power management state transitions, rate change, and receiver detection. When this signal transitions during entry and exit from P3 and PCLK is not running, then the signaling is asynchronous.
PWRPRESENT O H11 Indicates the presence of VBUS
CONFIGURATION PINS
TX_ONESZEROS I, PD M4 Active High. Used only when transmitting USB compliance pat-terns CP7 or CP8. Causes the transmitter to transmit an alternating sequence of 50 to 250 ones and 50 to 250 zeros—regardless of the state of the TX_DATA interface.
TX_DEEMPH1 I, PD, PU K11 Selects transmitter de-emphasis. When the MAC changes, the TUSB1310A starts to transmit with the new setting within 128 ns.
TX_DEEMPH0 L11 BIT 1 BIT 0 DESCRIPTION
0 0 –6-dB de-emphasis
0 1 –3.5-dB de-emphasis
1 0 No de-emphasis
1 1 Reserved
TX_MARGIN2 I, PD M11 Selects transmitter voltage levels
TX_MARGIN1 M10 BIT 2 BIT 1 BIT 0 TX_SWING DESCRIPTION
TX_MARGIN0 M9 0 0 0 0 Normal operating range
800 mV to 1200 mV
0 0 0 1 Normal operating range
400 mV to 700 mV
0 0 1 0 800 mV to 1200 mV
1 400 mV to 700 mV
0 1 0 0 700 mV to 900 mV
1 300 mV to 500 mV
0 1 1 0 400 mV to 600 mV
1 200 mV to 400 mV
1 Don't care 0 200 mV to 400 mV
1 1 100 mV to 200 mV
TX_SWING I, PD M5 Controls transmitter voltage swing level
0: Full swing
1: Half swing
RX_POLARITY I, PD C8 Active High. Tells PHY to do a polarity inversion on the received data. Inverted data show up on RX_DATA15-0 within 20 PCLK clocks after RX_POLARITY is asserted.
0: PHY does no polarity inversion
1: PHY does polarity inversion
RX_TERMINATION I, PD D3 Controls presence of receiver terminations
0: Terminations removed
1: Terminations present
RATE I, PU L6 Controls the link signaling rate
The RATE is always 1
ELAS_BUF_MODE I, PD C9 Selects elasticity buffer operating mode
0: Nominal half full buffer mode
1: Nominal empty buffer mode

3.3.2 ULPI

The ULPI (ultra low pin count interface) is a low pin count USB PHY to a Link-Layer Controller interface. The ULPI consists of the interface and the ULPI registers. The TUSB1310A device is always the master of the ULPI bus.

Table 3-4 ULPI Signal Descriptions

SIGNAL NAME TYPE BALL NO. DESCRIPTION
ULPI_CLK O P11 60-MHz interface clock. All ULPI signals are synchronous to ULPI_CLK. The ULPI_CLK is always a 60-MHz output of the TUSB1310A device. In low-power mode, the ULPI_CLK is not driven.
ULPI_DATA7 S, I/O, PD N6 Data bus. Driven to 00h by the Link when the ULPI bus is idle.
8-bit data timed on rising edge of ULPI_CLK
ULPI_DATA6 P6
ULPI_DATA5 N7
ULPI_DATA4 P7
ULPI_DATA3 N8
ULPI_DATA2 P8
ULPI_DATA1 P9
ULPI_DATA0 N9
ULPI_DIR O M7 Controls the direction of the ULPI_DATA bus
0: ULPI_DATA lines are inputs
1: ULPI_DATA lines are outputs
ULPI_STP S, I, PU M8 Active High. The Link must assert ULPI_STP to signal the end of a USB transmit packet or a register write operation. The ULPI_STP signal must be asserted in the cycle after the last data byte is presented on the bus. The ULPI_STP has an internal weak pullup to safeguard against false commands on the ULPI_DATA lines.
ULPI_NXT O N11 Active High. The PHY asserts ULPI_NXT to throttle all data types, except register read data and the RX CMD. The PHY also asserts ULPI_NXT and ULPI_DIR simultaneously to indicate USB receive activity, if ULPI_DIR was previously low. The PHY is not allowed to assert ULPI_NXT during the first cycle of the TX CMD driven by the Link.

3.3.3 Clocking

Table 3-5 Clock Signal Name Descriptions

SIGNAL NAME TYPE BALL NO. DESCRIPTION
XI I A12 Crystal Input. This pin is the clock reference input for the TUSB1310A. The TUSB1310A device supports either a crystal unit, or a 1.8-V clock input. Frequencies supported are 20, 25, 30, or 40 MHz.
XO O A11 Crystal output. If a 1.8-V clock input is connected to XI, XO must be left open.
CLKOUT O D10 OOBCLK is driven in U3 mode.

3.3.4 JTAG Interface

The JTAG Interface is used for board-level boundary scan. All digital IO support IEEE1149.1 boundary scan and SuperSpeed differential pairs support IEEE1149.6 boundary scan.

Table 3-6 JTAG Signal Name Descriptions

SIGNAL NAME TYPE BALL NO. DESCRIPTION
JTAG_TCK I, PU G11 JTAG test clock
JTAG_TMS I, PU D11 JTAG test mode select
JTAG_TDI I, PU E11 JTAG test data input
JTAG_TRSTN I, PD E12 JTAG test asynchronous reset. Active Low. An external pulldown is required for normal operation.
JTAG_TDO O F11 JTAG test data output

3.3.5 Reset and Output Control Interface

Table 3-7 Reset and Output Control Signal Descriptions

SIGNAL NAME TYPE BALL NO. DESCRIPTION
RESETN I J11 Active Low. Resets the transmitter and receiver. This signal is asynchronous.
OUT_ENABLE I L10 Active High. This can be connected to a 1.8-V power-on-reset signal on the PCB to avoid static current and signal contention during power up.
0: Disable all driver outputs while I/O powers are supplied, but internal control circuit powers are not present during power up.
1: Enable all driver outputs during normal operation.

3.3.6 Strap Options

Strapping pins are latched by reset deassertion in the TUSB1310A device.

Table 3-8 Strapping Options(1)

SIGNAL NAME TYPE BALL NO. DESCRIPTION
XTAL_DIS
(RX_ELECIDLE) 		S, I/O, PD F3 Selects an input clock source
0: Crystal Input
1: Clock Input
SSC_DIS
(TX_MARGIN0)		 S, I, PD M9 Spread spectrum clocking disable
0: SSC enable
1: SSC disable
PIPE_16BIT
(PHY_STATUS) 		S, I/O, PD E3 Selects PIPE
0: 16-bit PIPE SDR mode
Must be 0 at reset.
ISO_START
(ULPI_DATA7) 		S, I/O, PD N6 Active High. Puts PIPE into isolate mode. When in the isolate mode, TUSB1310A device does not respond to packet data present at TX_DATA15-0, TXDATAK1-0 inputs and presents a high impedance on the PCLK, RX_DATA15-0, RX_DATAK1-0, RX_VALID outputs. When in the isolate mode, the TUSB1310A device continues to respond to ULPI. When the isolate mode bit in ULPI register is cleared, the USB interfaces starts transmitting packet data on TX_DATA15-0 and driving PCLK, RX_DATA15-0, RX_DATA1-0, and RX_VALID.
ULPI_8BIT
(ULPI_DATA6) 		S, I/O, PD P6 Selects ULPI data bus bit width
0: 8-bit ULPI SDR mode
Must be set to 0.
REFCLKSEL1,
REFCLKSEL0
(ULPI_DATA5,
ULPI_DATA4) 		S, I/O, PD N7
P7		 Select input reference clock frequency for on-chip oscillator
00: 20 MHz on XI
01: 25 MHz on XI
10: 30 MHz on XI
11: 40 MHz on XI
(1) Signals in green have double function just before reset and after reset.

3.3.7 USB Interfaces

Table 3-9 USB Interface Signal Name Descriptions

SIGNAL NAME TYPE BALL NO. DESCRIPTION
SSTXP O H14 USB SuperSpeed transmitter differential pair
SSTXM J14
SSRXP I E14 USB SuperSpeed receiver differential pair
SSRXM F14
DP I/O P14 USB non-SuperSpeed differential pair
DM P13
VBUS I N12 USB VBUS pin
Connected through an external voltage divider

3.3.8 Special Connect

Table 3-10 Special Connect Signal Descriptions

SIGNAL NAME TYPE BALL NO. DESCRIPTION
R1EXT O L14 High precision external resistor used for calibration. The R1 value shall be 10 kΩ ±1% accuracy.
R1EXTRTN I L13 R1 ground reference. This pin is not connected to board ground.
VDDA1P1 P M14 Needs a 1-µF bypass capacitor
RSVD I/O D6 Must be left open.
D5
C13
C14
K4
J4
A14

3.3.9 Power and Ground

Table 3-11 Power and Ground Signal Descriptions

SIGNAL NAME TYPE BALL NO. DESCRIPTION
VDDA3P3 P P12 Analog 3.3-V power supply
VDDA1P8 P N14 Analog 1.8-V power supply
A13
C10
VDDA1P1 P C12 Analog 1.1-V power supply
K14
G13
G14
D14
C11
VDD1P8 P B2 C3 Digital IO 1.8-V power supply
D4 D7
D8 D9
E4 F4
G4 H4
L5 L4
M3 L7
L8 L9
VDD1P1 P A5 A10 Digital 1.1-V power supply
B6 B10
E1 F2
K2 L1
N5 P4
N10 P10
K13 D13
C4
VSSA G B14 B13 Analog ground
J13 H13
F13 E13
K12 L12
G12
D12
N13
M12
M13
VSSOSC G B12 Oscillator ground
If using a crystal, this must not be connected to PCB ground plane.
See Section 6.2.2 for guidelines.
If using an oscillator, this must be connected to PCB ground.
VSS G F6 F7 Digital ground
F8 F9
G6 G7
G8 G9
J6 J7
H6 H7
H8 H9
J8 J9
B11 F12