SN74AUP2G08

Name: SN74AUP2G08
Brand: TI
SKU: SN74AUP2G08
Price: 0.123 USD

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2 通道、2 输入、0.8V 至 3.6V 低功耗 (< 1uA) 与门

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数据表

document-pdfAcrobat SN74AUP2G08 Low-Power Dual 2-Input Positive-AND Gate 数据表 (Rev. E) (英语) PDF | HTML

SN74AUP2G08

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数据表

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产品详情

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

-4

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

-4

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

DSBGA (YFP)

1.8 mm² 1 x 1.8

DSBGA (YZP)

2.8125 mm² 2.25 x 1.25

UQFN (RSE)

2.25 mm² 1.5 x 1.5

VSSOP (DCU)

6.2 mm² 2 x 3.1

X2SON (DQE)

1.4 mm² 1.4 x 1

Wide operating VCC range of 0.8V to 3.6V
Low static-power consumption (ICC = 0.9µA max)
Low dynamic-power consumption (Cpd = 4.3pF typ at 3.3V)
Low noise – overshoot and undershoot <10% of VCC
Ioff supports partial-power-down mode operation
Schmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV Typ at 3.3V)
3.6V I/O tolerant to support mixed-mode signal operation
tpd = 5.9ns max at 3.3V
Latch-up performance exceeds 100mA per JESD 78, Class II

Wide operating VCC range of 0.8V to 3.6V
Low static-power consumption (ICC = 0.9µA max)
Low dynamic-power consumption (Cpd = 4.3pF typ at 3.3V)
Low noise – overshoot and undershoot <10% of VCC
Ioff supports partial-power-down mode operation
Schmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV Typ at 3.3V)
3.6V I/O tolerant to support mixed-mode signal operation
tpd = 5.9ns max at 3.3V
Latch-up performance exceeds 100mA per JESD 78, Class II

This dual 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A ● B in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when VCC = 0V, preventing damaging current backflow through the device when it is powered down.

This dual 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A ● B in positive logic.

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	类型	标题		下载最新的英语版本		日期
*	数据表	SN74AUP2G08 Low-Power Dual 2-Input Positive-AND Gate 数据表 (Rev. E)	PDF \| HTML			2024年 4月 29日
	应用简报	了解施密特触发器 (Rev. A)	PDF \| HTML	英语版 (Rev.A)	PDF \| HTML	2022年 12月 1日
	选择指南	Little Logic Guide 2018 (Rev. G)				2018年 7月 6日
	选择指南	Logic Guide (Rev. AB)				2017年 6月 12日
	应用手册	How to Select Little Logic (Rev. A)				2016年 7月 26日
	选择指南	逻辑器件指南 2014 (Rev. AA)		最新英语版本 (Rev.AB)		2014年 11月 17日
	选择指南	小尺寸逻辑器件指南 (Rev. E)		最新英语版本 (Rev.G)		2012年 7月 16日
	应用手册	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection				2004年 7月 8日