Inicio Convertidores de datos Convertidores analógico-digitales (ADC) ADC de alta velocidad (≥ 10 MSPS)
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Convertidores de datos
Convertidores analógico-digitales (ADC)
ADC de alta velocidad (≥ 10 MSPS)

ADC34J22

ACTIVO

Convertidor analógico a digital (ADC) de cuatro canales, 12 bits y 50 MSPS

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ADC34J22

ACTIVO
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Detalles del producto

Sample rate (max) (Msps) 50 Resolution (Bits) 12 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 450 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 491 Architecture Pipeline SNR (dB) 70.5 ENOB (bit) 11.4 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 50 Resolution (Bits) 12 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 450 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 491 Architecture Pipeline SNR (dB) 70.5 ENOB (bit) 11.4 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGZ) 48 49 mm² 7 x 7
  • Quad Channel
  • 12-Bit Resolution
  • Single 1.8-V Supply
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 69.6 dBFS, SFDR = 86 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 203 mW/Ch at 160 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither
  • JESD204B Serial Interface:
    • Subclass 0, 1, 2 Compliant up to 3.2 Gbps
    • Supports One Lane per ADC up to 160 MSPS
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 14-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)
  • Quad Channel
  • 12-Bit Resolution
  • Single 1.8-V Supply
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 69.6 dBFS, SFDR = 86 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 203 mW/Ch at 160 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither
  • JESD204B Serial Interface:
    • Subclass 0, 1, 2 Compliant up to 3.2 Gbps
    • Supports One Lane per ADC up to 160 MSPS
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 14-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)

The ADC34J2x are a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.

The ADC34J2x are a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.
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Documentación técnica

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Tipo Título Fecha
* Data sheet ADC34J2x Quad-Channel, 12-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with JESD204B Interface datasheet (Rev. A) PDF | HTML 29 ene 2015
EVM User's guide ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) 24 ago 2018

Diseño y desarrollo

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Placa de evaluación

DEV-ADC34J22 — Módulo de evaluación de DEV-ADC34J22

The DEV-ADC34J22 is a four-channel, 50MSPS ADC Module designed to integrate with Altera’s HSMC standard. The DEV-ADC34J22 features TI’s new JESD204B compliant ADC34J22 Analog Digital Converter (ADC), with clocking conditioning using TI’s LMK04828 jitter cleaner. It provides (...)

Desde: Dallas Logic Corporation
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Firmware

TI-JESD204-IP — JESD204 Rapid Design IP para FPGA conectadas a convertidores de datos de alta velocidad TI

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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Modelo de simulación

ADC34J45 IBIS Model

SBAM204.ZIP (79 KB) - IBIS Model
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Diseños de referencia

TIDA-00294 — Diseño de referencia de la interfaz de un extremo a diferencial activo de alto rendimiento para el A

This reference design uses the ADC34J22 12b 50Msps JESD204B data converter and the THS4541 fully differential amplifer to demonstrate how to design a high performance active interface for high speed ADCs.  This type of circuit can be used in sensor front end, motor control, and test and (...)
Desde: Dallas Logic Corporation
Design guide: PDF
Esquema: PDF
Paquete Pasadores Descargar
VQFN (RGZ) 48 Ver opciones
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