CY74FCT646T

ACTIVO

Transceptores de bus octal registrados con salidas de 3 estados

Detalles del producto

Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL Output type TTL Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family FCT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL Output type TTL Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family FCT Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 24 159.65 mm² 15.5 x 10.3 SSOP (DBQ) 24 51.9 mm² 8.65 x 6
  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Independent Register for A and B Buses
  • CY54FCT646T
    • 48-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT646T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current
  • 3-State Outputs

  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Independent Register for A and B Buses
  • CY54FCT646T
    • 48-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT646T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current
  • 3-State Outputs

The \x92FCT646T devices consist of a bus transceiver circuit with 3-state, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers as the appropriate clock pin goes to a high logic level. Output-enable (G\) and direction (DIR) inputs control the transceiver function. In the transceiver mode,data present at the high-impedance port can be stored in either the A or B register, or in both. Select controls (SAB, SBA) can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when G\ is low. In the isolation mode (G\ is high), A data can be stored in the B register and/or B data can be stored in the A register.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT646T devices consist of a bus transceiver circuit with 3-state, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers as the appropriate clock pin goes to a high logic level. Output-enable (G\) and direction (DIR) inputs control the transceiver function. In the transceiver mode,data present at the high-impedance port can be stored in either the A or B register, or in both. Select controls (SAB, SBA) can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when G\ is low. In the isolation mode (G\ is high), A data can be stored in the B register and/or B data can be stored in the A register.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Documentación técnica

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Tipo Título Fecha
* Data sheet 8-Bit Registered Transceivers With 3-State Outputs datasheet (Rev. A) 01 oct 2001
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
User guide CYFCT Parameter Measurement Information 02 abr 2001
Selection guide Advanced Bus Interface Logic Selection Guide 09 ene 2001

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

Guía del usuario: PDF | HTML
Paquete Pasadores Descargar
SOIC (DW) 24 Ver opciones
SSOP (DBQ) 24 Ver opciones

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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