The TMP/ SMJ320C40KGD DSP is a 32-bit, floating-point processor manufactured in 0.72-um, double-level
metal CMOS technology. It is the fourth generation of DSPs from Texas Instruments, and it is the world\x92s first
DSP designed for parallel processing. The on-chip parallel processing capabilities of the \x92C40 make the
floating-point performance required by many applications achievable and cost-effective.
The TMP/ SMJ320C40 is the first DSP with on-chip communication ports for processor-to-processor
communication using simple communication software with no external hardware. This allows connectivity with
no external glue logic. The communication ports remove I/O bottlenecks, and the independent smart-DMA
coprocessor is able to handle the CPU I/O requirements.
The features of the communication ports are:
- Six communication ports for direct interprocessor communication and processor I/O
- 20 MBps bidirectional interface on each communication port for high-speed and low-cost multiprocessor interface
- Separate input and output first-in, first-out (FIFO) buffers for I/ O and processor-to-processor communication
- Automatic arbitration and handshaking for direct processor-to-processor connection
The DMA coprocessor allows concurrent I/O and CPU processing for superior sustained CPU performance.
The key features of the DMA coprocessor:
- Link pointers that allow DMA channels to auto-initialize
- Parallel CPU operation and DMA transfers
- Six DMA channels support communication-port-to-memory data transfers
The TMP/SMJ320C40KGD CPU is configured for high-speed internal parallel processing. The key features of
the CPU are:
- Eight operations/ cycles
- 40-/ 32-bit floating-point / integer multiply
- 40-/32-bit floating-point/ integer arithmetic and logic unit (ALU) operation
- Two data accesses
- Two address-register updates
- IEEE floating-point conversion
- Division and square-root support
- \x92C30 assembly language compatibility
- Byte and halfword accessibility
Key factors in a parallel-processing implementation are the development tools that are available. The \x92C40 is
supported by a host of parallel-processing development tools for developing and simulating code and for
debugging parallel-processing systems. The code generation tools include:
- Optimizing ANSI C compiler with a runtime library that supports use of communication ports and DMA
- SPOX™, by Spectron Microsystems Incorporated, which provides parallel processing support as well as DMA and communication port drivers
- Assembler and linker with support for mapping program and data to parallel processors.
The simulation tools include:
- Parallel DSP system-level simulation, by Logic Modeling Corporation (LMC), which includes a hardware verification (HV) model and a full functional (FF) model
- TI software simulator with high-level language debugger interface for simulating a single processor
The hardware development and verification tools include:
- Parallel processor in-circuit emulator and high-level language debugger: XDS510™
- Parallel processor development system with four TMS320C40s, local and global memory, and communication port connections
For additional information when designing for cold temperature operation, please see Texas Instruments
application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature
number SGUA001.
The TMP/ SMJ320C40KGD DSP is a 32-bit, floating-point processor manufactured in 0.72-um, double-level
metal CMOS technology. It is the fourth generation of DSPs from Texas Instruments, and it is the world\x92s first
DSP designed for parallel processing. The on-chip parallel processing capabilities of the \x92C40 make the
floating-point performance required by many applications achievable and cost-effective.
The TMP/ SMJ320C40 is the first DSP with on-chip communication ports for processor-to-processor
communication using simple communication software with no external hardware. This allows connectivity with
no external glue logic. The communication ports remove I/O bottlenecks, and the independent smart-DMA
coprocessor is able to handle the CPU I/O requirements.
The features of the communication ports are:
- Six communication ports for direct interprocessor communication and processor I/O
- 20 MBps bidirectional interface on each communication port for high-speed and low-cost multiprocessor interface
- Separate input and output first-in, first-out (FIFO) buffers for I/ O and processor-to-processor communication
- Automatic arbitration and handshaking for direct processor-to-processor connection
The DMA coprocessor allows concurrent I/O and CPU processing for superior sustained CPU performance.
The key features of the DMA coprocessor:
- Link pointers that allow DMA channels to auto-initialize
- Parallel CPU operation and DMA transfers
- Six DMA channels support communication-port-to-memory data transfers
The TMP/SMJ320C40KGD CPU is configured for high-speed internal parallel processing. The key features of
the CPU are:
- Eight operations/ cycles
- 40-/ 32-bit floating-point / integer multiply
- 40-/32-bit floating-point/ integer arithmetic and logic unit (ALU) operation
- Two data accesses
- Two address-register updates
- IEEE floating-point conversion
- Division and square-root support
- \x92C30 assembly language compatibility
- Byte and halfword accessibility
Key factors in a parallel-processing implementation are the development tools that are available. The \x92C40 is
supported by a host of parallel-processing development tools for developing and simulating code and for
debugging parallel-processing systems. The code generation tools include:
- Optimizing ANSI C compiler with a runtime library that supports use of communication ports and DMA
- SPOX™, by Spectron Microsystems Incorporated, which provides parallel processing support as well as DMA and communication port drivers
- Assembler and linker with support for mapping program and data to parallel processors.
The simulation tools include:
- Parallel DSP system-level simulation, by Logic Modeling Corporation (LMC), which includes a hardware verification (HV) model and a full functional (FF) model
- TI software simulator with high-level language debugger interface for simulating a single processor
The hardware development and verification tools include:
- Parallel processor in-circuit emulator and high-level language debugger: XDS510™
- Parallel processor development system with four TMS320C40s, local and global memory, and communication port connections
For additional information when designing for cold temperature operation, please see Texas Instruments
application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature
number SGUA001.
x
Test-Access Port (JTAG)