Inicio Lógica y traducción de voltaje Traductores de tensión y desplazadores de nivel Traductores de tensión con control de dirección
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Lógica y traducción de voltaje
Traductores de tensión y desplazadores de nivel
Traductores de tensión con control de dirección

SN54SLC8T245-SEP

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Traductor de nivel de 0.65 V a 3.3 V, de 8 bits, con tolerancia a la radiación y control de direcció

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SN54SLC8T245-SEP

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Detalles del producto

Technology family SLC Applications RGMII Bits (#) 8 High input voltage (min) (V) 0.4555 High input voltage (max) (V) 3.6 Vout (min) (V) 0.65 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 70 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Space Operating temperature range (°C) -55 to 125
Technology family SLC Applications RGMII Bits (#) 8 High input voltage (min) (V) 0.4555 High input voltage (max) (V) 3.6 Vout (min) (V) 0.65 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 70 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Space Operating temperature range (°C) -55 to 125
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4

  • VID V62/22604

  • Radiation tolerant:
    • Single event latch-up (SEL) immune up to 43 MeV-cm 2 /mg at 125°C
    • Total ionizing dose (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 20 krad(Si)
  • Qualified, fully configurable dual-rail design allows each port to operate with a power supply range from 0.65 V to 3.6 V
  • Operating temperature from –55°C to +125°C
  • Multiple direction-control pins allows simultaneous up and down translation
  • Up to 380 Mbps support when translating from 1.8 V to 3.3 V
  • V CC isolation feature that effectively isolates both buses in a power-down scenario
  • Partial power-down mode to limit backflow current in a power-down scenario
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 8000-V human-body model
    • 1000-V charged-device model

  • VID V62/22604

  • Radiation tolerant:
    • Single event latch-up (SEL) immune up to 43 MeV-cm 2 /mg at 125°C
    • Total ionizing dose (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 20 krad(Si)
  • Qualified, fully configurable dual-rail design allows each port to operate with a power supply range from 0.65 V to 3.6 V
  • Operating temperature from –55°C to +125°C
  • Multiple direction-control pins allows simultaneous up and down translation
  • Up to 380 Mbps support when translating from 1.8 V to 3.3 V
  • V CC isolation feature that effectively isolates both buses in a power-down scenario
  • Partial power-down mode to limit backflow current in a power-down scenario
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 8000-V human-body model
    • 1000-V charged-device model

The SN54SLC8T245-SEP device is an 8-bit non-inverting bus transceiver that resolves voltage level mismatch between devices operating at the latest voltage nodes (0.7 V, 0.8 V, and 0.9 V) and devices operating at industry standard voltage nodes (1.8 V, 2.5 V, and 3.3 V).

The device operates by using two independent power-supply rails (V CCA and V CCB) that operate as low as 0.65 V. Data pins A1 through A8 are designed to track V CCA, which accepts any supply voltage from 0.65 V to 3.6 V. Data pins B1 through B8 are designed to track V CCB, which accepts any supply voltage from 0.65 V to 3.6 V.

The SN54SLC8T245-SEP device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (DIR1 and DIR2). The output-enable ( OE) input is used to disable the outputs so the buses are effectively isolated.

The SN54SLC8T245-SEP device is designed so the control pins (DIR and OE) are referenced to V CCA.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The V CC isolation feature is designed so that if either V CC input supply is below 100 mV, all level shifter outputs are disabled and placed into a high-impedance state.

To put the level shifter I/Os in the high-impedance state during power up or power down, tie OE to V CCA through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.

The SN54SLC8T245-SEP device is an 8-bit non-inverting bus transceiver that resolves voltage level mismatch between devices operating at the latest voltage nodes (0.7 V, 0.8 V, and 0.9 V) and devices operating at industry standard voltage nodes (1.8 V, 2.5 V, and 3.3 V).

The device operates by using two independent power-supply rails (V CCA and V CCB) that operate as low as 0.65 V. Data pins A1 through A8 are designed to track V CCA, which accepts any supply voltage from 0.65 V to 3.6 V. Data pins B1 through B8 are designed to track V CCB, which accepts any supply voltage from 0.65 V to 3.6 V.

The SN54SLC8T245-SEP device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (DIR1 and DIR2). The output-enable ( OE) input is used to disable the outputs so the buses are effectively isolated.

The SN54SLC8T245-SEP device is designed so the control pins (DIR and OE) are referenced to V CCA.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The V CC isolation feature is designed so that if either V CC input supply is below 100 mV, all level shifter outputs are disabled and placed into a high-impedance state.

To put the level shifter I/Os in the high-impedance state during power up or power down, tie OE to V CCA through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.
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Documentación técnica

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Tipo Título Fecha
* Data sheet SN54SLC8T245-SEP8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs datasheet (Rev. B) PDF | HTML 05 dic 2023
* Radiation & reliability report SN54SLC8T245-SEP Production Flow and Reliability Report PDF | HTML 20 oct 2022
* Radiation & reliability report SN54SLC8T245-SEP Single Event Effects Report PDF | HTML 12 oct 2022
* Radiation & reliability report SN54SLC8T245-SEP Total Ionizing Dose (TID) PDF | HTML 03 oct 2022

Diseño y desarrollo

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Placa de evaluación

AVCLVCDIRCNTRL-EVM — EVM genérico para dispositivo de traducción bidireccional controlado por dirección compatible con AV

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

Guía del usuario: PDF
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Placa de evaluación

ALPHA-3P-ADM-VA600-SPACE-AMD — Kit Alpha Data ADM-VA600 con núcleo AMD Versal XQRVC1902 ACAP y productos TI tolerantes a la radiaci

Este es un factor de forma VPX de 6U en el que destaca el SoC/FPGA adaptable AMD-Xilinx® Versal AI Core XQRVC1902. El ADM-VA600 tiene un diseño de placa modular con un conector FMC+, DDR4 DRAM y monitorización del sistema. La mayoría de los componentes son dispositivos de alimentación, (...)

Desde: Alpha Data Parallel Systems Ltd.
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Modelo de simulación

SN54SLC8T245-SEP IBIS Model (Rev. B)

SCEM795B.ZIP (82 KB) - IBIS Model
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TSSOP (PW) 24 Ver opciones
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