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Circuitos integrados HDMI, DisplayPort y MIPI

SN65DSI83

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Puente LVDS de enlace único MIPI® DSI de canal único y circuito integrado Flatlink™

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SN65DSI83

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Detalles del producto

Type Bridge Protocols LVDS, MIPI DSI Rating Catalog Speed (max) (Gbps) 4 Supply voltage (V) 1.8 Operating temperature range (°C) -40 to 85
Type Bridge Protocols LVDS, MIPI DSI Rating Catalog Speed (max) (Gbps) 4 Supply voltage (V) 1.8 Operating temperature range (°C) -40 to 85
NFBGA (ZXH) 64 25 mm² 5 x 5
  • Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Single channel DSI receiver configurable for 1, 2, 3, or 4 D-PHY data lanes per channel operating up to 1 Gbps/lane
  • Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats
  • Max resolution up to 60 fps WUXGA 1920 × 1200 at 18 bpp and 24 bpp color with reduced blanking. suitable for 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp
  • FlatLink™ output for single-link LVDS
  • Supports single channel DSI to single-link LVDS operating mode
  • LVDS Output Clock Range of 25 MHz to 154 MHz
  • LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
  • 1.8-V main VCC power supply
  • Low power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI ultra-low power state (ULPS) support
  • LVDS channel swap, LVDS PIN order reverse feature for ease of PCB routing
  • ESD rating ±2 kV (HBM)
  • Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)
  • Temperature range: –40°C to 85°C
  • Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Single channel DSI receiver configurable for 1, 2, 3, or 4 D-PHY data lanes per channel operating up to 1 Gbps/lane
  • Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats
  • Max resolution up to 60 fps WUXGA 1920 × 1200 at 18 bpp and 24 bpp color with reduced blanking. suitable for 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp
  • FlatLink™ output for single-link LVDS
  • Supports single channel DSI to single-link LVDS operating mode
  • LVDS Output Clock Range of 25 MHz to 154 MHz
  • LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
  • 1.8-V main VCC power supply
  • Low power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI ultra-low power state (ULPS) support
  • LVDS channel swap, LVDS PIN order reverse feature for ease of PCB routing
  • ESD rating ±2 kV (HBM)
  • Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)
  • Temperature range: –40°C to 85°C

The SN65DSI83 DSI to FlatLink bridge device features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18 bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink-compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link.

The SN65DSI83 device can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24 bpp with reduced blanking. The SN65DSI83 device is also suitable for applications using 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry-compliant interface technology, the SN65DSI83 device is compatible with a wide range of microprocessors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI defined ultra-low power state (ULPS) support.

The SN65DSI83 device is implemented in a small outline 5-mm × 5-mm nFBGA at 0.5-mm pitch package, and operates across a temperature range from –40°C to 85°C.

The SN65DSI83 DSI to FlatLink bridge device features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18 bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink-compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link.

The SN65DSI83 device can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24 bpp with reduced blanking. The SN65DSI83 device is also suitable for applications using 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry-compliant interface technology, the SN65DSI83 device is compatible with a wide range of microprocessors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI defined ultra-low power state (ULPS) support.

The SN65DSI83 device is implemented in a small outline 5-mm × 5-mm nFBGA at 0.5-mm pitch package, and operates across a temperature range from –40°C to 85°C.
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Documentación técnica

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Tipo Título Fecha
* Data sheet SN65DSI83 MIPI DSI Bridge to FLAT LINK LVDS Single Channel DSI to SL LVDS Bridge datasheet (Rev. I) 01 oct 2020
* User guide HSSC MicroStar BGA Discontinued and Redesigned 08 may 2022
Application note Troubleshooting SN65DSI8x - Tips and Tricks 27 ago 2018
EVM User's guide SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and Implementation Guide 17 nov 2015
Application note SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation Guide (Rev. A) 11 abr 2013
Application note SN65DSI8x Video Configuration Guide and Configuration Tool Software Users Manual (Rev. B) 08 abr 2013

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

SN65DSI83EVM — SN65DSI83 Módulo de evaluación de puente MIPI® DSI a LVDS y circuito integrado FlatLink™

The SN65DSI83EVM evaluation module (EVM) is a printed circuit board (PCB) that helps customers implement the SN65DSI85 device in system hardware.  This EVM can be used as a hardware reference design for any implementation using the SN65DSI83 device. This EVM includes (...)
Guía del usuario: PDF
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Modelo de simulación

SN65DSI83 IBIS Model

SLLM202.ZIP (254 KB) - IBIS Model
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Modelo de simulación

SN65DSI85 Hspice Model

SLLJ007.ZIP (1092 KB) - HSpice Model
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
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Paquete Pasadores Descargar
NFBGA (ZXH) 64 Ver opciones
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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