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Circuitos integrados LVDS, M-LVDS y PECL

SN65LVDM176

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Transceptor LVDM semidúplex

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SN65LVDM176

ACTIVO
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Detalles del producto

Function Transceiver Protocols LVDM, LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal LVDM, LVTTL Output signal LVDM, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols LVDM, LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal LVDM, LVTTL Output signal LVDM, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Low-Voltage Differential Driver and Receiver for Half-Duplex Operation
  • Designed for Signaling Rates of 400 Mbit/s
  • ESD Protection Exceeds 15 kV on Bus Pins
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 50- Load
  • Valid Output With as Little as 50 mV Input Voltage Difference
  • Propagation Delay Times
    • Driver: 1.7 ns Typ
    • Receiver: 3.7 ns Typ
  • Power Dissipation at 200 MHz
    • Driver: 50 mW Typical
    • Receiver: 60 mW Typical
  • LVTTL Levels Are 5-V Tolerant
  • Bus Pins Are High Impedance When Disabled or With VCC Less Than 1.5 V
  • Open-Circuit Fail-Safe Receiver
  • Surface-Mount Packaging
    • D Package (SOIC)
    • DGK Package (MSOP)

PowerPAD is a trademark of Texas Instruments.
  • Low-Voltage Differential Driver and Receiver for Half-Duplex Operation
  • Designed for Signaling Rates of 400 Mbit/s
  • ESD Protection Exceeds 15 kV on Bus Pins
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 50- Load
  • Valid Output With as Little as 50 mV Input Voltage Difference
  • Propagation Delay Times
    • Driver: 1.7 ns Typ
    • Receiver: 3.7 ns Typ
  • Power Dissipation at 200 MHz
    • Driver: 50 mW Typical
    • Receiver: 60 mW Typical
  • LVTTL Levels Are 5-V Tolerant
  • Bus Pins Are High Impedance When Disabled or With VCC Less Than 1.5 V
  • Open-Circuit Fail-Safe Receiver
  • Surface-Mount Packaging
    • D Package (SOIC)
    • DGK Package (MSOP)

PowerPAD is a trademark of Texas Instruments.

The SN65LVDM176 is a differential line driver and receiver configured as a transceiver that uses low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbit/s. These circuits are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50- load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of less than 50 mV with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of this device and signaling technique is for half-duplex or multiplex baseband data transmission over controlled impedance media of approximately 100- characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics).

The SN65LVDM176 is characterized for operation from \x9640°C to 85°C.

The SN65LVDM176 is a differential line driver and receiver configured as a transceiver that uses low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbit/s. These circuits are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50- load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of less than 50 mV with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of this device and signaling technique is for half-duplex or multiplex baseband data transmission over controlled impedance media of approximately 100- characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics).

The SN65LVDM176 is characterized for operation from \x9640°C to 85°C.
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Documentación técnica

star =Principal documentación para este producto seleccionada por TI
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Tipo Título Fecha
* Data sheet High-Speed Differential Line Transceiver datasheet (Rev. D) 03 ago 2000
Application note An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C) PDF | HTML 22 jun 2023
Application brief How Far, How Fast Can You Operate MLVDS? 06 ago 2018
Application note Transmission at 200 Mbps in VME Card Cage Using LVDM (Rev. A) 04 ene 2002
Application note SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) 20 nov 2001

Diseño y desarrollo

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Modelo de simulación

SN65LVDM176 IBIS Model

SLLM011.ZIP (50 KB) - IBIS Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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