Inicio Interfaz Circuitos integrados LVDS, M-LVDS y PECL
Inicio
Interfaz
Circuitos integrados LVDS, M-LVDS y PECL

SN65LVDS108

ACTIVO

1:8 Búfer de salida del ventilador del reloj LVDS

Haga su pedido ahora
Hoja de datos

SN65LVDS108

ACTIVO
Hoja de datos Haga su pedido ahora

Detalles del producto

Function Receiver, Repeater Protocols LVDS Number of transmitters 8 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal LVDS Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver, Repeater Protocols LVDS Number of transmitters 8 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal LVDS Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DBT) 38 62.08 mm² 9.7 x 6.4
  • One Line Receiver and Eight Line Drivers Configured as an 8-Port LVDS Repeater
  • Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
  • Enabling Logic Allows Individual Control of Each Driver Output, Plus All Outputs
  • Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100- Load
  • Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Termination Networks
  • Propagation Delay Times < 4.7 ns
  • Output Skew Less Than 300 ps and Part-to-Part Skew Less Than 1.5 ns
  • Total Power Dissipation at 200 MHz Typically Less Than 330 mW With 8 Channels Enabled
  • Driver Outputs or Receiver Input Equals High Impedance When Disabled or With VCC < 1.5 V
  • Bus-Pin ESD Protection Exceeds 12 kV
  • Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch
  • One Line Receiver and Eight Line Drivers Configured as an 8-Port LVDS Repeater
  • Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
  • Enabling Logic Allows Individual Control of Each Driver Output, Plus All Outputs
  • Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100- Load
  • Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Termination Networks
  • Propagation Delay Times < 4.7 ns
  • Output Skew Less Than 300 ps and Part-to-Part Skew Less Than 1.5 ns
  • Total Power Dissipation at 200 MHz Typically Less Than 330 mW With 8 Channels Enabled
  • Driver Outputs or Receiver Input Equals High Impedance When Disabled or With VCC < 1.5 V
  • Bus-Pin ESD Protection Exceeds 12 kV
  • Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch

The SN65LVDS108 is configured as one differential line receiver connected to eight differential line drivers. Individual output enables are provided for each output and an additional enable is provided for all outputs.

The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)

The intended application of this device, and the LVDS signaling technique, is for point-to-point or point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is particularly advantageous for implementing system clock or data distribution trees.

The SN65LVDS108 is characterized for operation from –40°C to 85°C.

The SN65LVDS108 is configured as one differential line receiver connected to eight differential line drivers. Individual output enables are provided for each output and an additional enable is provided for all outputs.

The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)

The intended application of this device, and the LVDS signaling technique, is for point-to-point or point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is particularly advantageous for implementing system clock or data distribution trees.

The SN65LVDS108 is characterized for operation from –40°C to 85°C.
open-in-new Buscar otro/a Circuitos integrados LVDS, M-LVDS y PECL
Descargar Ver vídeo con transcripción Video

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 1
Tipo Título Fecha
* Data sheet 8-Port LVDS Repeater datasheet (Rev. E) 02 feb 2005

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

SN65LVDS108 IBIS Model (Rev. A)

SLLC064A.ZIP (9 KB) - IBIS Model
Descargar
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Solicitar
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Ver opciones
Paquete Pasadores Descargar
TSSOP (DBT) 38 Ver opciones
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Ver todos los temas del foro en inglés

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos