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Circuitos integrados LVDS, M-LVDS y PECL

SN65LVDS180

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Transceptor LVDS único de dúplex completo

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SN65LVDS180

ACTIVO
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Detalles del producto

Function Transceiver Protocols LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 150, 400 Input signal LVDS, LVTTL Output signal LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 150, 400 Input signal LVDS, LVTTL Output signal LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 14 51.9 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Meets or Exceeds the Requirements of ANSI
    TIA/EIA-644-1995 Standard
  • Full-Duplex Signaling Rates up to 150 Mbps
  • Bus-Pin ESD Exceeds 12 kV
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Typical
    Output Voltages of 350 mV and a 100-Ω Load
  • Propagation Delay Times
    • Driver: 1.7 ns Typical
    • Receiver: 3.7 ns Typical
  • Power Dissipation at 200 MHz
    • Driver: 25 mW Typical
    • Receiver: 60 mW Typical
  • LVTTL Input Levels Are 5-V Tolerant
  • Receiver Maintains High Input Impedance With
    VCC < 1.5 V
  • Receiver Has Open-Circuit Fail Safe
  • Meets or Exceeds the Requirements of ANSI
    TIA/EIA-644-1995 Standard
  • Full-Duplex Signaling Rates up to 150 Mbps
  • Bus-Pin ESD Exceeds 12 kV
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Typical
    Output Voltages of 350 mV and a 100-Ω Load
  • Propagation Delay Times
    • Driver: 1.7 ns Typical
    • Receiver: 3.7 ns Typical
  • Power Dissipation at 200 MHz
    • Driver: 25 mW Typical
    • Receiver: 60 mW Typical
  • LVTTL Input Levels Are 5-V Tolerant
  • Receiver Maintains High Input Impedance With
    VCC < 1.5 V
  • Receiver Has Open-Circuit Fail Safe

The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 devices are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The TIA/EIA-644 standard-compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100-Ω load and receipt of 100-mV signals with up to 1 V of ground potential difference between a transmitter and receiver.

These devices offer various driver, receiver, and enabling combinations in industry-standard footprints. Because these devices are intended for use in simplex or distributed simplex bus structures, the driver enable function does not put the differential outputs into a high-impedance state but rather disconnects the input and reduces the quiescent power used by the device. For these functions with a high-impedance driver output, see the SN65LVDM series of devices. All devices are characterized for operation from –40°C to 85°C.

The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 devices are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The TIA/EIA-644 standard-compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100-Ω load and receipt of 100-mV signals with up to 1 V of ground potential difference between a transmitter and receiver.

These devices offer various driver, receiver, and enabling combinations in industry-standard footprints. Because these devices are intended for use in simplex or distributed simplex bus structures, the driver enable function does not put the differential outputs into a high-impedance state but rather disconnects the input and reduces the quiescent power used by the device. For these functions with a high-impedance driver output, see the SN65LVDM series of devices. All devices are characterized for operation from –40°C to 85°C.
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Documentación técnica

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* Data sheet SN65LVDSxxx High-Speed Differential Line Drivers and Receivers datasheet (Rev. R) PDF | HTML 22 ene 2016
Application brief LVDS to Improve EMC in Motor Drives 27 sep 2018
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 ago 2018
Application brief How to Terminate LVDS Connections with DC and AC Coupling 16 may 2018

Diseño y desarrollo

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Modelo de simulación

SN65LVDS180 IBIS Model

SLLM006.ZIP (50 KB) - IBIS Model
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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