Inicio Interfaz Circuitos integrados LVDS, M-LVDS y PECL
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Circuitos integrados LVDS, M-LVDS y PECL

SN65LVDT41-EP

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SN65LVDT41-EP

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Detalles del producto

Function Transceiver Protocols LVDS Number of transmitters 4 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 125 Input signal LVDS, LVTTL Output signal LVDS, LVTTL Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 125
Function Transceiver Protocols LVDS Number of transmitters 4 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 125 Input signal LVDS, LVTTL Output signal LVDS, LVTTL Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 125
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • Integrated 110- Nominal Receiver Line Termination Resistor
  • Operate From a Single 3.3-V Supply
  • Greater Than 125-Mbps Data Rate
  • Flow-Through Pinout
  • LVTTL-Compatible Logic I/Os
  • ESD Protection on Bus Pins Exceeds 12 kV
  • Meet or Exceed Requirements of ANSI/TIA/EIA-644A Standard for LVDS
  • 20-Pin Thin Shrink Small-Outline Package (PW) With 26-Mil Terminal Pitch
  • APPLICATIONS
    • Memory Stick™ Interface Extensions With Long Interconnects Between Host and
      Memory Stick
    • Serial Peripheral Interface™ (SPI™) Interface Extension to Allow Long Interconnects
      Between Master and Slave
    • MultiMediaCard™ (MMC) Interface in SPI Mode
    • General-Purpose Asymmetric Bidirectional Communication

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
Serial Peripheral Interface, SPI are trademarks of Motorola.
MultiMediaCard is a trademark of MultiMediaCard Association.
Memory Stick is a trademark of Sony.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • Integrated 110- Nominal Receiver Line Termination Resistor
  • Operate From a Single 3.3-V Supply
  • Greater Than 125-Mbps Data Rate
  • Flow-Through Pinout
  • LVTTL-Compatible Logic I/Os
  • ESD Protection on Bus Pins Exceeds 12 kV
  • Meet or Exceed Requirements of ANSI/TIA/EIA-644A Standard for LVDS
  • 20-Pin Thin Shrink Small-Outline Package (PW) With 26-Mil Terminal Pitch
  • APPLICATIONS
    • Memory Stick™ Interface Extensions With Long Interconnects Between Host and
      Memory Stick
    • Serial Peripheral Interface™ (SPI™) Interface Extension to Allow Long Interconnects
      Between Master and Slave
    • MultiMediaCard™ (MMC) Interface in SPI Mode
    • General-Purpose Asymmetric Bidirectional Communication

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
Serial Peripheral Interface, SPI are trademarks of Motorola.
MultiMediaCard is a trademark of MultiMediaCard Association.
Memory Stick is a trademark of Sony.

The SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package. It is designed to be used at the Memory Stick™ end of an LVDS-based Memory Stick interface extension.

The SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package. It is designed to be used at the host end of an LVDS-based Memory Stick interface extension.

The SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package. It is designed to be used at the Memory Stick™ end of an LVDS-based Memory Stick interface extension.

The SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package. It is designed to be used at the host end of an LVDS-based Memory Stick interface extension.
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Documentación técnica

star =Principal documentación para este producto seleccionada por TI
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Tipo Título Fecha
* Data sheet SN65LVDT14-EP, SN65LVDT41-EP datasheet 07 jun 2005
* Radiation & reliability report SN65LVDT41QPWREP Reliability Report 06 feb 2015
Application brief LVDS to Improve EMC in Motor Drives 27 sep 2018
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 ago 2018
Application brief How to Terminate LVDS Connections with DC and AC Coupling 16 may 2018

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

SN65LVDT41 IBIS Model

SLLC120.ZIP (7 KB) - IBIS Model
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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TSSOP (PW) 20 Ver opciones
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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