Inicio Lógica y traducción de voltaje Traductores de tensión y desplazadores de nivel Traductores de tensión con control de dirección
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Lógica y traducción de voltaje
Traductores de tensión y desplazadores de nivel
Traductores de tensión con control de dirección

SN74AVC1T45

ACTIVO

Transceptor de bus de alimentación doble de un solo bit con selector de nivel de tensión configurabl

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SN74AXC1T45 ACTIVO Transceptor de bus de alimentación doble de un bit Pin-to-pin upgrade with a wider voltage range and improved performance

SN74AVC1T45

ACTIVO
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Detalles del producto

Technology family AVC Applications GPIO Bits (#) 1 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 500 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 20 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AVC Applications GPIO Bits (#) 1 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 500 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 20 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 6 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 6 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 6 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1
  • Available in the Texas Instruments NanoFree™ package
  • Fully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply range
  • VCC isolation feature – if either VCC input is at GND, then both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • ±12mA output drive at 3.3V
  • I/Os are 4.6V tolerant
  • Ioff supports partial-power-down mode operation
  • Typical maximum data rates
    • 500Mbps (1.8V to 3.3V translation)
    • 320Mbps (<1.8V to 3.3V translation)
    • 320Mbps (translate to 2.5V or 1.8V)
    • 280Mbps (translate to 1.5V)
    • 240Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • ±2000V Human Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • ±1000V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ package
  • Fully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply range
  • VCC isolation feature – if either VCC input is at GND, then both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • ±12mA output drive at 3.3V
  • I/Os are 4.6V tolerant
  • Ioff supports partial-power-down mode operation
  • Typical maximum data rates
    • 500Mbps (1.8V to 3.3V translation)
    • 320Mbps (<1.8V to 3.3V translation)
    • 320Mbps (translate to 2.5V or 1.8V)
    • 280Mbps (translate to 1.5V)
    • 240Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • ±2000V Human Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • ±1000V Charged-Device Model (C101)

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage, bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC1T45 is designed so that the DIR input is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage, bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC1T45 is designed so that the DIR input is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
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Documentación técnica

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* Data sheet SN74AVC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. I) PDF | HTML 20 mar 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in CMOS Output Buffers PDF | HTML 14 may 2024
EVM User's guide Generic AVC and LVC Direction Controlled Translation EVM (Rev. B) 30 jul 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 abr 2021
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 30 abr 2015
Test report TI Power Reference Design for Xilinx® Artix®-7 (AC701) 12 may 2014
User guide PMP7977 User's Guide 11 sep 2013
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
More literature LCD Module Interface Application Clip 09 may 2003
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 20 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 07 jul 1999
Application note AVC Logic Family Technology and Applications (Rev. A) 26 ago 1998

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

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Modelo de simulación

SN74AVC1T45 IBIS Model (Rev. B)

SCEM436B.ZIP (118 KB) - IBIS Model
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Disposición de la PCB

PMP7977 PCB

TIDU151.PDF (6781 KB)
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Muchos diseños de referencia de TI incluyen SN74AVC1T45

Utilice nuestra herramienta de selección de diseños de referencia para revisar e identificar los diseños que mejor se adaptan a su aplicación y parámetros.

Ver diseños de referencia
Paquete Pasadores Descargar
DSBGA (YZP) 6 Ver opciones
SOT-23 (DBV) 6 Ver opciones
SOT-5X3 (DRL) 6 Ver opciones
SOT-SC70 (DCK) 6 Ver opciones
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Pedidos y calidad

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  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
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  • Lugar de fabricación
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