The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed
for asynchronous communication between data buses. When data is
transmitted from the A to B bus, a parity bit is generated. When data
is transmitted from the B to A bus with its corresponding parity bit,
the parity-error (
) output will
indicate whether or not an error in the B data has occurred. The
output-enable (
, 
) inputs can be used to disable the
device so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY)
output and monitors the parity of the I/O ports with an
open-collector parity-error () flag. can
be either passed, sampled, stored, or cleared from the latch using
the latch-enable (
) and clear
(
) control
inputs. When both and are low, data is transferred from
the A bus to the B bus and inverted parity is generated. Inverted
parity is a forced error condition which gives the designer more
system diagnostic capability. The SN74BCT29854 provides inverting
logic.
The SN74BCT29854 is characterized for operation from 0°C to 70°C.
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | 8-Bit To 9-Bit Parity Bus Transceiver datasheet | 01 nov 1993 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 26 jul 2021 | ||
| Selection guide | Logic Guide (Rev. AB) | 12 jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 dic 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 ene 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 ago 2002 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 01 ago 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 oct 1996 | ||
| Application note | Live Insertion | 01 oct 1996 |
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.
| Paquete | Pasadores | Descargar |
|---|---|---|
| SOIC (DW) | 24 | Ver opciones |
El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.
Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI.