These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers.
Output-enable (OEAB and 
)
inputs are provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided to select whether
real-time or stored data is transferred. The circuitry used for
select control eliminates the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real-time
data. A low input selects real-time data, and a high input selects
stored data. Figure 1 illustrates the four fundamental bus-management
functions that can be performed with the ´BCT652.
Data on the A or B data bus, or both, can be stored in the
internal D-type flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs regardless of the select-
or enable-control pins. When SAB and SBA are in the real-time
transfer mode, it is possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and . In this configuration each output
reinforces its input. Therefore, when all other data sources to the
two sets of bus lines are at high impedance, each set of bus lines
remain at its last state.
The SN54BCT652 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT652 is characterized for operation from 0°C to 70°C.
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | Octal Bus Transceivers And Registers With 3-State Outputs datasheet (Rev. A) | 01 nov 1993 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 26 jul 2021 | ||
| Selection guide | Logic Guide (Rev. AB) | 12 jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 dic 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 ene 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 ago 2002 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 01 ago 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 oct 1996 | ||
| Application note | Live Insertion | 01 oct 1996 |
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.
| Paquete | Pasadores | Descargar |
|---|---|---|
| SOIC (DW) | 24 | Ver opciones |
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