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Lógica y traducción de voltaje
Traductores de tensión y desplazadores de nivel
Traductores de tensión con control de dirección

SN74LVC1T45

ACTIVO

Transceptor de bus de alimentación doble de un solo bit con selector de nivel de tensión configurabl

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SN74LVC1T45

ACTIVO
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Detalles del producto

Technology family LVC Applications GPIO Bits (#) 1 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 300 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 4 Features Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family LVC Applications GPIO Bits (#) 1 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 300 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 4 Features Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 6 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 6 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 6 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1 USON (DPK) 6 2.56 mm² 1.6 x 1.6
  • ESD protection exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ package
  • Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V power-supply range
  • VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • Low power consumption, 4-µA maximum ICC
  • ±24-mA output drive at 3.3 V
  • Ioff supports partial-power-down mode operation
  • Maximum data rates
    • 420 Mbps (3.3-V to 5-V translation)
    • 210 Mbps (translate to 3.3 V)
    • 140 Mbps (translate to 2.5 V)
    • 75 Mbps (translate to 1.8 V)
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ package
  • Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V power-supply range
  • VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • Low power consumption, 4-µA maximum ICC
  • ±24-mA output drive at 3.3 V
  • Ioff supports partial-power-down mode operation
  • Maximum data rates
    • 420 Mbps (3.3-V to 5-V translation)
    • 210 Mbps (translate to 3.3 V)
    • 140 Mbps (translate to 2.5 V)
    • 75 Mbps (translate to 1.8 V)
  • Latch-up performance exceeds 100 mA per JESD 78, Class II

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry is always active on both A and B ports and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC1T45 is designed so that the DIR input is powered by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry is always active on both A and B ports and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC1T45 is designed so that the DIR input is powered by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
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Documentación técnica

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* Data sheet SN74LVC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. M) PDF | HTML 18 nov 2022
EVM User's guide Generic AVC and LVC Direction Controlled Translation EVM (Rev. B) 30 jul 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 abr 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 dic 2002
Application note Texas Instruments Little Logic Application Report 01 nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 dic 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note LVC Characterization Information 01 dic 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

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Placa de evaluación

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Guía del usuario: PDF
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The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

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Guía del usuario: PDF | HTML
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Modelo de simulación

HSPICE MODEL OF SN74LVC1T45

SCEJ231.ZIP (94 KB) - HSpice Model
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Modelo de simulación

SN74LVC1T45 IBIS Model (Rev. C)

SCEM401C.ZIP (99 KB) - IBIS Model
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Modelo de simulación

SN74LVC1T45 TINA-TI Reference Design (Rev. A)

SCEM545A.TSC (23812 KB) - TINA-TI Reference Design
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Modelo de simulación

SN74LVC1T45 TINA-TI Spice Model (Rev. A)

SCEM546A.ZIP (7 KB) - TINA-TI Spice Model
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Paquete Pasadores Descargar
DSBGA (YZP) 6 Ver opciones
SOT-23 (DBV) 6 Ver opciones
SOT-5X3 (DRL) 6 Ver opciones
SOT-SC70 (DCK) 6 Ver opciones
USON (DPK) 6 Ver opciones
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Pedidos y calidad

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