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SN75LVDT1422

COMPRA POR ÚLTIMA VEZ

Serializador y deserializador dúplex completo

Detalles del producto

Function SerDes Protocols Channel-Link I Supply voltage (V) 3.3 Signaling rate (MBits) 1400 Input signal LVDS Output signal LVDS, LVTTL Rating Catalog Operating temperature range (°C) -10 to 70
Function SerDes Protocols Channel-Link I Supply voltage (V) 3.3 Signaling rate (MBits) 1400 Input signal LVDS Output signal LVDS, LVTTL Rating Catalog Operating temperature range (°C) -10 to 70
TQFP (PAG) 64 144 mm² 12 x 12
  • 10 MHz to 100 MHz Shift Clock Support
  • 175 Mbytes/sec In TX/RX Modes
  • Reduces Cable Size, Cost, and System EMI
  • Bidirectional Data Communication
  • Total Power < 360 mW Typ at 100-MHz Worst Case Pattern
  • Power-Down Mode: < 500 µW Typ
  • No External Components Required for PLL
  • Inputs and Outputs Compatible with TIA/EIA-644 LVDS Standard
  • ESD Rating > 5 kV (HBM)
  • Integrated Termination Resistor
  • Supports Spread Spectrum Clocking
  • 64-Pin TQFP Package (PAG)
  • APPLICATIONS
    • Flash Memory Cards
    • Plain Paper Copiers
    • Printers

  • 10 MHz to 100 MHz Shift Clock Support
  • 175 Mbytes/sec In TX/RX Modes
  • Reduces Cable Size, Cost, and System EMI
  • Bidirectional Data Communication
  • Total Power < 360 mW Typ at 100-MHz Worst Case Pattern
  • Power-Down Mode: < 500 µW Typ
  • No External Components Required for PLL
  • Inputs and Outputs Compatible with TIA/EIA-644 LVDS Standard
  • ESD Rating > 5 kV (HBM)
  • Integrated Termination Resistor
  • Supports Spread Spectrum Clocking
  • 64-Pin TQFP Package (PAG)
  • APPLICATIONS
    • Flash Memory Cards
    • Plain Paper Copiers
    • Printers

The SN75LVDT1422 Full Duplex Serializer/Deserializer incorporates a 14-bit serializer and a 14-bit deserializer. Operation of the serializer is independent of the operation of the deserializer. The 14-bit serializer accepts 14 TTL input lines and generates 2 LVDS high-speed serial streams plus one LVDS clock signal. The 14-bit deserializer accepts 3 LVDS input signals (2 high-speed serial streams and one LVDS clock signal) and drives out 14 TTL data signals plus one TTL clock.

The serializer loads 14 data bits into registers upon the rising or falling edge of the input clock signal (CLK IN). Rising or falling edge operation can be selected via the R/F select pin for the transmitter only. The frequency of CLK IN is multiplied seven times and then used to unload the data registers in 7-bit slices. The two high-speed serial streams and a phase-locked clock (TCLK±) are then output to LVDS output drivers. The frequency of TCLK± is the same as the input clock, CLK IN.

The deserializer accepts data on two high-speed LVDS data lines. High-speed data is received and loaded into registers at the rate seven times the LVDS input clock (RCLK±). The data is then unloaded to a 14-bit wide LVTTL parallel bus at the RCLK± rate. The SN75LVDT1422 presents valid data on the falling edge of the output clock (CLK OUT).

The SN75LVDT1422 provides three termination resistors for the differential LVDS inputs thus minimizing cost, and board space, while providing better overall signal integrity (SI). The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user interventions are as follows:

Possible use of the TX ENABLE and RX ENABLE feature. Both the TX and RX ENABLE circuits are active-high inputs that independently enable the serializer and deserializer. When TX is disabled, the LVDS outputs go to high impedance. When RX is disabled, the TTL outputs go to a known low state.

The SN75LVDT1422 is characterized for operation over the free-air temperature range of -10°C to 70°C.

The SN75LVDT1422 Full Duplex Serializer/Deserializer incorporates a 14-bit serializer and a 14-bit deserializer. Operation of the serializer is independent of the operation of the deserializer. The 14-bit serializer accepts 14 TTL input lines and generates 2 LVDS high-speed serial streams plus one LVDS clock signal. The 14-bit deserializer accepts 3 LVDS input signals (2 high-speed serial streams and one LVDS clock signal) and drives out 14 TTL data signals plus one TTL clock.

The serializer loads 14 data bits into registers upon the rising or falling edge of the input clock signal (CLK IN). Rising or falling edge operation can be selected via the R/F select pin for the transmitter only. The frequency of CLK IN is multiplied seven times and then used to unload the data registers in 7-bit slices. The two high-speed serial streams and a phase-locked clock (TCLK±) are then output to LVDS output drivers. The frequency of TCLK± is the same as the input clock, CLK IN.

The deserializer accepts data on two high-speed LVDS data lines. High-speed data is received and loaded into registers at the rate seven times the LVDS input clock (RCLK±). The data is then unloaded to a 14-bit wide LVTTL parallel bus at the RCLK± rate. The SN75LVDT1422 presents valid data on the falling edge of the output clock (CLK OUT).

The SN75LVDT1422 provides three termination resistors for the differential LVDS inputs thus minimizing cost, and board space, while providing better overall signal integrity (SI). The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user interventions are as follows:

Possible use of the TX ENABLE and RX ENABLE feature. Both the TX and RX ENABLE circuits are active-high inputs that independently enable the serializer and deserializer. When TX is disabled, the LVDS outputs go to high impedance. When RX is disabled, the TTL outputs go to a known low state.

The SN75LVDT1422 is characterized for operation over the free-air temperature range of -10°C to 70°C.

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Documentación técnica

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Tipo Título Fecha
* Data sheet 14-Bit Full Duplex Serializer/Deserializer datasheet 14 jun 2005
User guide ADS5500/5541/5542/5520/5521/5522 14-&12-Bit Single Channel ADC w/LVDT1422 Output 26 jul 2006

Diseño y desarrollo

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Modelo de simulación

SN75LVDT1422 IBIS Model

SLLC261.ZIP (21 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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TQFP (PAG) 64 Ver opciones

Pedidos y calidad

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  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
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