SN65HVD1040A-Q1
- Qualified for Automotive Applications
- AEC-Q100 Test Guidance With the Following:
- Device Temperature Grade 0: –40°C to +150°C Ambient Operating Temperature
- Device HBM ESD Classification Level: 3A Level for All Pins Except 5, 6, and 7
3B Level for Pins 5, 6 and 7 - Device CDM ESD Classification Level C6
- Device MM ESD Classification Level M3
- Improved Drop-In Replacement for TJA1040
- Meets or Exceeds the Requirements of ISO 11898-5
- GIFT/ICT Compliant
- ESD Protection up to ±12 kV (Human-Body Model) on Bus Pins
- Low-Current Standby Mode With Bus Wake-Up, <12 µA Maximum
- High Electromagnetic Compliance (EMC)
- Bus-Fault Protection of –27 V to 40 V
- Dominant Time-Out Function
- Thermal Shutdown Protection
- SPLIT Voltage Source for Common-Mode Stabilization of Bus Through Split Termination
- Digital Inputs Compatible With 3.3-V and 5-V Microprocessors.
- Power-Up and Power-Down Glitch-Free Bus Inputs and Outputs
- High Input Impedance With Low VCC
- Monotonic Outputs During Power Cycling
- APPLICATIONS
- GMW3122 Dual-Wire CAN Physical Layers
- SAE J2284 High-Speed CAN for Automotive Applications
- SAE J1939 Standard Data Bus Interface
- ISO 11783 Standard Data Bus Interface
- NMEA 2000 Standard Data Bus Interface
(1) The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the units bps (bits per second)
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The SN65HVD1040A device meets or exceeds the specifications of the ISO 11898 standard for use in applications employing a Controller Area Network (CAN). The device is qualified for use in automotive applications.
As a CAN transceiver, this device provides differential transmit capability to the bus and differential receive capability to a CAN controller at signaling rates up to 1 megabit per second (Mbps)(1).
Designed for operation in especially harsh environments, the SN65HVD1040A-Q1 features cross-wire, overvoltage, and loss of ground protection from –27 V to 40 V, overtemperature protection, a –12-V to 12-V common-mode range, and can withstand voltage transients according to ISO 7637.
STB (pin 8) provides two different modes of operation: high-speed mode or low-current standby mode. The high-speed mode of operation is selected by connecting STB (pin 8) to ground.
If a high logic level is applied to the STB pin of the SN65HVD1040A-Q1, the device enters a low-current standby mode, while the receiver remains active in a low-power bus-monitor standby mode.
In the low-current standby mode, a dominant bit greater than 5 µs on the bus is passed by the bus-monitor circuit to the receiver output. The local protocol controller may then reactivate the device when it needs to transmit to the bus.
A dominant time-out circuit in the SN65HVD1040A-Q1 prevents the driver from blocking network communication with a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no rising edge is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then reset by the next rising edge on TXD.
SPLIT (pin 5) is available as a VCC/2 common-mode bus voltage bias for a split-termination network (see Application and Implementation).
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技術資料
| 種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
|---|---|---|---|---|---|---|
| * | データシート | SN65HVD1040A-Q1 EMC-Optimized High-Speed CAN Transceiver データシート (Rev. C) | PDF | HTML | 2016年 8月 30日 |
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| パッケージ | ピン数 | ダウンロード |
|---|---|---|
| SOIC (D) | 8 | オプションの表示 |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 材質成分
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
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