AFE58JD32

활성

42mW/ch 전력, 디지털 복조기, JESD204B 및 LVDS 인터페이스를 갖춘 32채널 초음파 AFE

제품 상세 정보

Device type Receiver Number of input channels 32 Active supply current (typ) (mA) 40 Supply voltage (max) (V) 3.3 Operating temperature range (°C) -40 to 85 Interface type JESD204B, LVDS Features Analog Front End (AFE) Rating Catalog
Device type Receiver Number of input channels 32 Active supply current (typ) (mA) 40 Supply voltage (max) (V) 3.3 Operating temperature range (°C) -40 to 85 Interface type JESD204B, LVDS Features Analog Front End (AFE) Rating Catalog
NFBGA (ZBV) 289 225 mm² 15 x 15
  • 32-Channel, AFE for Ultrasound Applications:
    • Input Attenuator, LNA, LPF, ADC,
      Digital I/Q Demodulator and CW Mixer
    • Digital Time Gain Compensation (DTGC)
    • Total Gain Range: 12 dB to 51 dB
    • Linear Input Range: 800 mVPP
  • Input Attenuator With DTGC:
    • 8-dB to 0-dB Attenuation With 0.125-dB Step
    • Supports Matched Impedance for:
      • 50-Ω to 800-Ω Source Impedance
  • Low-Noise Amplifier (LNA) With DTGC:
    • 20-dB to 51-dB Gain With 0.125-dB Step
    • Low Input Current Noise: 1.2 pA/√Hz
  • 3rd-Order, Linear-Phase, Low-Pass Filter (LPF):
    • 5 MHz, 7.5 MHz, 10 MHz, and 12.5 MHz
  • 16 ADCs Converting at 12-Bit, 80 MSPS or 10-bit, 100 MSPS:
    • Each ADC Converts Two Sets of Inputs at Half Rate
    • 12-Bit ADC: 72-dBFS SNR
    • 10-Bit ADC: 61-dBFS SNR
  • Optimized for Noise and Power:
    • 35 mW/Ch at 2.1 nV/√Hz, 40 MSPS
    • 42 mW/Ch at 1.4 nV/√Hz, 40 MSPS
    • 52 mW/Ch at 1.3 nV/√Hz, 40 MSPS
    • 60 mW/Ch in CW Mode
  • Excellent Device-to-Device Gain Matching:
    • ±0.5 dB (Typical)
  • Low Harmonic Distortion: –55 dBc
  • Fast and Consistent Overload Recovery
  • Continuous Wave (CW) Path With:
    • Low Close-In Phase Noise of –151 dBc/Hz
      at 1-kHz Frequency Offset Off 2.5-MHz Carrier
    • Phase Resolution: λ / 16
    • Supports 16X CW Clock
    • 12-dB Suppression on Third and Fifth Harmonics
  • Digital I/Q Demodulator After ADC:
    • Decimation Filter M = 1 to 63
    • Data Throughput Reduction After Decimation
    • On-Chip RAM with 32 Preset Profiles
  • LVDS Interface With a Speed Up to 1 Gbps
  • 5-Gbps JESD Interface:
    • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD Lane
  • Small Package: 15-mm × 15-mm NFBGA-289
  • 32-Channel, AFE for Ultrasound Applications:
    • Input Attenuator, LNA, LPF, ADC,
      Digital I/Q Demodulator and CW Mixer
    • Digital Time Gain Compensation (DTGC)
    • Total Gain Range: 12 dB to 51 dB
    • Linear Input Range: 800 mVPP
  • Input Attenuator With DTGC:
    • 8-dB to 0-dB Attenuation With 0.125-dB Step
    • Supports Matched Impedance for:
      • 50-Ω to 800-Ω Source Impedance
  • Low-Noise Amplifier (LNA) With DTGC:
    • 20-dB to 51-dB Gain With 0.125-dB Step
    • Low Input Current Noise: 1.2 pA/√Hz
  • 3rd-Order, Linear-Phase, Low-Pass Filter (LPF):
    • 5 MHz, 7.5 MHz, 10 MHz, and 12.5 MHz
  • 16 ADCs Converting at 12-Bit, 80 MSPS or 10-bit, 100 MSPS:
    • Each ADC Converts Two Sets of Inputs at Half Rate
    • 12-Bit ADC: 72-dBFS SNR
    • 10-Bit ADC: 61-dBFS SNR
  • Optimized for Noise and Power:
    • 35 mW/Ch at 2.1 nV/√Hz, 40 MSPS
    • 42 mW/Ch at 1.4 nV/√Hz, 40 MSPS
    • 52 mW/Ch at 1.3 nV/√Hz, 40 MSPS
    • 60 mW/Ch in CW Mode
  • Excellent Device-to-Device Gain Matching:
    • ±0.5 dB (Typical)
  • Low Harmonic Distortion: –55 dBc
  • Fast and Consistent Overload Recovery
  • Continuous Wave (CW) Path With:
    • Low Close-In Phase Noise of –151 dBc/Hz
      at 1-kHz Frequency Offset Off 2.5-MHz Carrier
    • Phase Resolution: λ / 16
    • Supports 16X CW Clock
    • 12-dB Suppression on Third and Fifth Harmonics
  • Digital I/Q Demodulator After ADC:
    • Decimation Filter M = 1 to 63
    • Data Throughput Reduction After Decimation
    • On-Chip RAM with 32 Preset Profiles
  • LVDS Interface With a Speed Up to 1 Gbps
  • 5-Gbps JESD Interface:
    • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD Lane
  • Small Package: 15-mm × 15-mm NFBGA-289

The AFE58JD32 device is a highly-integrated, analog front-end solution specifically designed for ultrasound systems where high performance, low power, and small size are required.

The AFE58JD32 is an integrated analog front-end (AFE) optimized for medical ultrasound application. The device is realized through a multichip module (MCM) with three dies: two voltage-controlled amplifier (VCA) dies and one analog-to-digital converter (ADC) die. Each VCA die has 16 channels and the ADC die converts all of the 32 channels.

Each channel in the VCA die is configured in either of two modes: time gain compensation (TGC) mode or continuous wave (CW) mode. In TGC mode, each channel includes an input attenuator (ATTEN), a low-noise amplifier (LNA) with variable-gain, and a third-order, low-pass filter (LPF). The attenuator supports an attenuation range of 8 dB to 0 dB, and the LNA supports gain ranges from 20 dB to 51 dB. The LPF cutoff frequency can be configured at 5 MHz, 7.5 MHz, 10 MHz, or 12.5 MHz to support ultrasound applications with different frequencies. In CW mode, each channel includes an LNA with a fixed gain of 18 dB, and a low-power passive mixer with 16 selectable phase delays. Different phase delays can be applied to each analog input signal to perform an on-chip beamforming operation. A harmonic filter in the CW mixer suppresses the third and fifth harmonic to enhance the sensitivity of the CW Doppler measurement.

The ADC die has 16 physical ADCs. Each ADC converts two sets of outputs – one from each VCA die. The ADC is configured to operate with a resolution of 12 bits or 10 bits. The ADC resolution can be traded off with conversion rate, and operates at maximum speeds of 80 MSPS and 100 MSPS at 12-bit and 10-bit resolution, respectively. The ADC is designed to scale its power with sampling rate. The output interface of the ADC comes out through a low-voltage differential signaling (LVDS) which can easily interface with low-cost field-programmable gate arrays (FPGAs).

The AFE58JD32 includes an optional digital demodulator and JESD204B data packing blocks. The digital in-phase and quadrature (I/Q) demodulator with programmable decimation filters accelerates computationally-intensive algorithms at low power. The device also supports an optional JESD204B interface that runs up to 5-Gbps and further reduces the circuit-board routing challenges in high-channel count systems.

The AFE58JD32 also allows various power and noise combinations to be selected for optimizing system performance. Therefore, this device is a suitable ultrasound AFE solution for systems with strict battery-life requirements.

The AFE58JD32 device is a highly-integrated, analog front-end solution specifically designed for ultrasound systems where high performance, low power, and small size are required.

The AFE58JD32 is an integrated analog front-end (AFE) optimized for medical ultrasound application. The device is realized through a multichip module (MCM) with three dies: two voltage-controlled amplifier (VCA) dies and one analog-to-digital converter (ADC) die. Each VCA die has 16 channels and the ADC die converts all of the 32 channels.

Each channel in the VCA die is configured in either of two modes: time gain compensation (TGC) mode or continuous wave (CW) mode. In TGC mode, each channel includes an input attenuator (ATTEN), a low-noise amplifier (LNA) with variable-gain, and a third-order, low-pass filter (LPF). The attenuator supports an attenuation range of 8 dB to 0 dB, and the LNA supports gain ranges from 20 dB to 51 dB. The LPF cutoff frequency can be configured at 5 MHz, 7.5 MHz, 10 MHz, or 12.5 MHz to support ultrasound applications with different frequencies. In CW mode, each channel includes an LNA with a fixed gain of 18 dB, and a low-power passive mixer with 16 selectable phase delays. Different phase delays can be applied to each analog input signal to perform an on-chip beamforming operation. A harmonic filter in the CW mixer suppresses the third and fifth harmonic to enhance the sensitivity of the CW Doppler measurement.

The ADC die has 16 physical ADCs. Each ADC converts two sets of outputs – one from each VCA die. The ADC is configured to operate with a resolution of 12 bits or 10 bits. The ADC resolution can be traded off with conversion rate, and operates at maximum speeds of 80 MSPS and 100 MSPS at 12-bit and 10-bit resolution, respectively. The ADC is designed to scale its power with sampling rate. The output interface of the ADC comes out through a low-voltage differential signaling (LVDS) which can easily interface with low-cost field-programmable gate arrays (FPGAs).

The AFE58JD32 includes an optional digital demodulator and JESD204B data packing blocks. The digital in-phase and quadrature (I/Q) demodulator with programmable decimation filters accelerates computationally-intensive algorithms at low power. The device also supports an optional JESD204B interface that runs up to 5-Gbps and further reduces the circuit-board routing challenges in high-channel count systems.

The AFE58JD32 also allows various power and noise combinations to be selected for optimizing system performance. Therefore, this device is a suitable ultrasound AFE solution for systems with strict battery-life requirements.

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기술 문서

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모두 보기1
유형 직함 날짜
* Data sheet AFE58JD32 32-Channel Ultrasound AFE With 35-mW/Channel Power, 2.1 nV/√Hz Noise, 12-Bit, 40-MSPS or 10-Bit, 50-MSPS Output, Passive CW Mixer, LVDS and JESD204B Interface, and Digital Demodulator datasheet (Rev. A) PDF | HTML 2018/04/19

설계 및 개발

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평가 보드

AFE58JD32EVM — AFE58JD32 디지털 디모듈레이터가 포함된 32채널 초음파 AFE 평가 모듈

The AFE58JD32 is a highly-integrated, analog front-end (AFE) solution specifically designed for ultrasound systems where high performance and small size are required. The device integrates a complete time-gain-control (TGC) imaging path and a continuous-wave Doppler (CWD) path. The 32-channel (...)

시뮬레이션 모델

AFE58JD32 IBIS Model (Rev. A)

SBAM334A.ZIP (58 KB) - IBIS Model
시뮬레이션 툴

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TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
패키지 다운로드
NFBGA (ZBV) 289 옵션 보기

주문 및 품질

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  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
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  • 조립 위치

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