제품 상세 정보

Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5, 12 Protocols Analog Ron (typ) (Ω) 30 CON (typ) (pF) 5 Supply current (typ) (µA) 2 Bandwidth (MHz) 200 Operating temperature range (°C) -55 to 125 Features Break-before-make Input/output continuous current (max) (mA) 25 Rating Catalog Drain supply voltage (max) (V) 10 Supply voltage (max) (V) 10
Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5, 12 Protocols Analog Ron (typ) (Ω) 30 CON (typ) (pF) 5 Supply current (typ) (µA) 2 Bandwidth (MHz) 200 Operating temperature range (°C) -55 to 125 Features Break-before-make Input/output continuous current (max) (mA) 25 Rating Catalog Drain supply voltage (max) (V) 10 Supply voltage (max) (V) 10
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Wide Analog-Input-Voltage Range . . . 0V to 10V
  • Low "ON" Resistance
    • 45 (Typ) . . . . VCC = 4.5V
    • 35 (Typ) . . . . VCC = 6V
    • 30 (Typ) . .1fcVCC = 9V
  • Fast Switching and Propagation Delay Times
  • Low "OFF" Leakage Current
  • Built-In "Break-Before-Make" Switching
  • Suitable for Sample and Hold Applications
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • HC Types
    • 2V to 10V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Wide Analog-Input-Voltage Range . . . 0V to 10V
  • Low "ON" Resistance
    • 45 (Typ) . . . . VCC = 4.5V
    • 35 (Typ) . . . . VCC = 6V
    • 30 (Typ) . .1fcVCC = 9V
  • Fast Switching and Propagation Delay Times
  • Low "OFF" Leakage Current
  • Built-In "Break-Before-Make" Switching
  • Suitable for Sample and Hold Applications
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • HC Types
    • 2V to 10V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

The CD74HC4016 contains four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.

Each switch has two input/output terminals (nY, nZ) and an active high enable input (nE). Current through the switch will not cause additional VCC current provided the analog voltage is maintained between VCC and GND.

The CD74HC4016 contains four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.

Each switch has two input/output terminals (nY, nZ) and an active high enable input (nE). Current through the switch will not cause additional VCC current provided the analog voltage is maintained between VCC and GND.

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기술 문서

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모두 보기16
유형 직함 날짜
* Data sheet CD74HC4016 datasheet (Rev. C) 2004/08/02
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022/06/02
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021/12/01
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996/05/01
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996/04/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

인터페이스 어댑터

LEADED-ADAPTER1 — TI의 5, 8, 10, 16 및 24핀 리드 패키지의 빠른 테스트를 위한 DIP 헤더 어댑터에 대한 표면 실장

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

사용 설명서: PDF
TI.com에서 구매할 수 없습니다
패키지 다운로드
PDIP (N) 14 옵션 보기
SOIC (D) 14 옵션 보기
TSSOP (PW) 14 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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