제품 상세 정보

Resolution (Bits) 14 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 125 Features Low Power Rating Catalog Interpolation 1x Power consumption (typ) (mW) 310 SFDR (dB) 82 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Ext, Int
Resolution (Bits) 14 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 125 Features Low Power Rating Catalog Interpolation 1x Power consumption (typ) (mW) 310 SFDR (dB) 82 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Ext, Int
TQFP (PFB) 48 81 mm² 9 x 9
  • 125MSPS UPDATE RATE
  • SINGLE SUPPLY: +3.3V or +5V
  • HIGH SFDR: 78dB at fOUT = 10MHz
  • LOW GLITCH: 2pV-s
  • LOW POWER: 310mW
  • INTERNAL REFERENCE
  • POWER-DOWN MODE: 23mW
  • APPLICATIONS
    • COMMUNICATIONS:
      • Base Stations, WLL, WLAN
      • Baseband I/Q Modulation
    • MEDICAL/TEST INSTRUMENTATION
    • ARBITRARY WAVEFORM GENERATORS (ARB)
    • DIRECT DIGITAL SYNTHESIS (DDS)

All trademarks are the property of their respective owners.

  • 125MSPS UPDATE RATE
  • SINGLE SUPPLY: +3.3V or +5V
  • HIGH SFDR: 78dB at fOUT = 10MHz
  • LOW GLITCH: 2pV-s
  • LOW POWER: 310mW
  • INTERNAL REFERENCE
  • POWER-DOWN MODE: 23mW
  • APPLICATIONS
    • COMMUNICATIONS:
      • Base Stations, WLL, WLAN
      • Baseband I/Q Modulation
    • MEDICAL/TEST INSTRUMENTATION
    • ARBITRARY WAVEFORM GENERATORS (ARB)
    • DIRECT DIGITAL SYNTHESIS (DDS)

All trademarks are the property of their respective owners.

The DAC2904 is a monolithic, 14-bit, dual-channel, high-speed Digital-to-Analog Converter (DAC), and is optimized to provide high dynamic performance while dissipating only 310mW.

Operating with high update rates of up to 125MSPS, the DAC2904 offers exceptional dynamic performance, and enables the generation of very-high output frequencies suitable for “Direct IF” applications. The DAC2904 has been optimized for communications applications in which separate I and Q data are processed while maintaining tight-gain and offset matching.

Each DAC has a high-impedance differential-current output, suitable for single-ended or differential analog-output configurations.

The DAC2904 combines high dynamic performance with a high update rate to create a cost-effective solution for a wide variety of waveform-synthesis applications:

  • Pin compatibility between family members provides 10-bit (DAC2900), 12-bit (DAC2902), and 14-bit (DAC2904) resolution.
  • Pin compatible to the AD9767 dual DAC.
  • Gain matching is typically 0.5% of full-scale, and offset matching is specified at 0.02% max.
  • The DAC2904 utilizes an advanced CMOS process; the segmented architecture minimizes output-glitch energy, and maximizes the dynamic performance.
  • All digital inputs are +3.3V and +5V logic compatible. The DAC2904 has an internal reference circuit, and allows use in a multiplying configuration.

The DAC2904 is available in a TQFP-48 package, and is specified over the extended industrial temperature range of –40°C to +85°C.

The DAC2904 is a monolithic, 14-bit, dual-channel, high-speed Digital-to-Analog Converter (DAC), and is optimized to provide high dynamic performance while dissipating only 310mW.

Operating with high update rates of up to 125MSPS, the DAC2904 offers exceptional dynamic performance, and enables the generation of very-high output frequencies suitable for “Direct IF” applications. The DAC2904 has been optimized for communications applications in which separate I and Q data are processed while maintaining tight-gain and offset matching.

Each DAC has a high-impedance differential-current output, suitable for single-ended or differential analog-output configurations.

The DAC2904 combines high dynamic performance with a high update rate to create a cost-effective solution for a wide variety of waveform-synthesis applications:

  • Pin compatibility between family members provides 10-bit (DAC2900), 12-bit (DAC2902), and 14-bit (DAC2904) resolution.
  • Pin compatible to the AD9767 dual DAC.
  • Gain matching is typically 0.5% of full-scale, and offset matching is specified at 0.02% max.
  • The DAC2904 utilizes an advanced CMOS process; the segmented architecture minimizes output-glitch energy, and maximizes the dynamic performance.
  • All digital inputs are +3.3V and +5V logic compatible. The DAC2904 has an internal reference circuit, and allows use in a multiplying configuration.

The DAC2904 is available in a TQFP-48 package, and is specified over the extended industrial temperature range of –40°C to +85°C.

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기술 문서

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모두 보기5
유형 직함 날짜
* Data sheet Dual, 14-Bit, 125 MSPS Digital-to-Analog Converter datasheet (Rev. C) 2004/10/14
Application note Wideband Complementary Current Output DAC Single-Ended Interface (Rev. A) 2015/05/08
User guide TSW3000 Demo Kit (Rev. B) 2005/11/20
User guide TSW3000 Demo Kit (Rev. A) 2005/09/26
EVM User's guide DAC290x-EVM: Demo Board (Rev. B) 2005/09/20

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 모델

DAC2904 IBIS Model for 3.3V

SLWC052.ZIP (6 KB) - IBIS Model
시뮬레이션 모델

DAC2904 IBIS Model for 5V

SLWC053.ZIP (5 KB) - IBIS Model
계산 툴

MATCHGAIN-CALC — 광대역 콤퍼레이터 전류 출력 DAC-SE 인터페이스: 게인 및 규정 준수 전압 스윙에 대한 충돌 일치

NOTE: Calculator software is available when downloading the application note.
  • Click on "abstract" to view abstract of document.
  • Open the ZIP file to extract the calculator tool.
  • Open the PDF file to view the application note.

High-speed digital-to-analog converters (DACs) most often use a (...)

시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
패키지 다운로드
TQFP (PFB) 48 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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