제품 상세 정보

Resolution (Bits) 14 Number of DAC channels 1 Interface type Parallel CMOS Sample/update rate (Msps) 400 Features High Performance Rating Catalog Interpolation 2x, 4x Power consumption (typ) (mW) 435 SFDR (dB) 85 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Int
Resolution (Bits) 14 Number of DAC channels 1 Interface type Parallel CMOS Sample/update rate (Msps) 400 Features High Performance Rating Catalog Interpolation 2x, 4x Power consumption (typ) (mW) 435 SFDR (dB) 85 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Int
HTQFP (PHP) 48 81 mm² 9 x 9
  • 200-MSPS Maximum Input Data Rate
  • 400-MSPS Maximum Update Rate DAC
  • 76-dBc SFDR Over Full First Nyquist Zone With Single Tone Input Signal (Fout = 21 MHz)
  • 74-dBc ACPR W-CDMA at 15.36 MHz IF
  • 69-dBc ACPR W-CDMA at 30.72 MHz IF
  • Selectable 2x or 4x Interpolation Filter
    • Linear Phase
    • 0.05-dB Passband Ripple
    • 80-dB Stopband Attenuation
    • Stopband Transition 0.4-0.6 Fdata
    • Interpolation Filters Configurable in Either Low-Pass or High-Pass Mode, Allows For Selection Higher Order Image
  • On-chip 2x/4x PLL Clock Multiplier, PLL Bypass Mode
  • Differential Scalable Current Outputs: 2 mA to 20 mA
  • On-Chip 1.2-V Reference
  • 1.8-V Digital and 3.3-V Analog Supply Operation
  • 1.8/3.3-V CMOS Compatible Interface
  • Power Dissipation: 435 mW at 400 MSPS
  • Package: 48-Pin TQFP
  • APPLICATIONS
    • Cellular Base Transceiver Station Transmit Channel
      • CDMA: W-CDMA, CDMA2000, IS-95
      • TDMA: GSM, IS-136, EDGE/UWC-136
    • Test and Measurement: Arbitrary Waveform Generation
    • Direct Digital Synthesis (DDS)
    • Cable Modem Termination System

Excel is a trademark of Microsoft Corporation.
CommsDAC and PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.

  • 200-MSPS Maximum Input Data Rate
  • 400-MSPS Maximum Update Rate DAC
  • 76-dBc SFDR Over Full First Nyquist Zone With Single Tone Input Signal (Fout = 21 MHz)
  • 74-dBc ACPR W-CDMA at 15.36 MHz IF
  • 69-dBc ACPR W-CDMA at 30.72 MHz IF
  • Selectable 2x or 4x Interpolation Filter
    • Linear Phase
    • 0.05-dB Passband Ripple
    • 80-dB Stopband Attenuation
    • Stopband Transition 0.4-0.6 Fdata
    • Interpolation Filters Configurable in Either Low-Pass or High-Pass Mode, Allows For Selection Higher Order Image
  • On-chip 2x/4x PLL Clock Multiplier, PLL Bypass Mode
  • Differential Scalable Current Outputs: 2 mA to 20 mA
  • On-Chip 1.2-V Reference
  • 1.8-V Digital and 3.3-V Analog Supply Operation
  • 1.8/3.3-V CMOS Compatible Interface
  • Power Dissipation: 435 mW at 400 MSPS
  • Package: 48-Pin TQFP
  • APPLICATIONS
    • Cellular Base Transceiver Station Transmit Channel
      • CDMA: W-CDMA, CDMA2000, IS-95
      • TDMA: GSM, IS-136, EDGE/UWC-136
    • Test and Measurement: Arbitrary Waveform Generation
    • Direct Digital Synthesis (DDS)
    • Cable Modem Termination System

Excel is a trademark of Microsoft Corporation.
CommsDAC and PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.

The DAC5674 is a 14-bit resolution high-speed digital-to-analog converter (DAC) with integrated 4x-interpolation filter, on-board clock multiplier, and on-chip voltage reference. The device has been designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct-digital synthesis (DDS) and waveform reconstruction in test and measurement applications.

The 4x-interpolation filter is implemented as a cascade of two 2x-interpolation filters, each of which can be configured for either low-pass or high-pass response. This enables the user to select one of the higher order images present at multiples of the input data rate clock while maintaining a low date input rate. The resulting high IF output frequency allows the user to omit the conventional first mixer in heterodyne transmitter architectures and directly up-convert to RF using only one mixer, thereby reducing system complexity and costs.

In 4x-interpolation low-pass response mode, the DACs excellent spurious free dynamic range (SFDR) at intermediate frequencies located in the first Nyquist zone (up to 40 MHz) allows for multicarrier transmission in cellular base transceiver stations (BTS). The low-pass interpolation mode thereby relaxes image filter requirements by filtering out the images in the adjacent Nyquist zones.

The DAC5674 PLL clock multiplier controls all internal clocks for the digital filters and DAC core. The differential clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock divider of the PLL ensures that the digital filters operate at the correct clock frequencies.

The DAC5674 operates from an analog supply voltage of 3.3 V and a digital supply voltage of 1.8 V. The digital I/Os are 1.8-V and 3.3-V CMOS compatible. Power dissipation is 500 mW at maximum operating conditions. The DAC5674 provides a nominal full-scale differential current-output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The device has been specifically designed for a differential transformer coupled output with a 50- doubly terminated load. For a 20-mA full-scale output current both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2-dBm output power) are supported. The latter configuration is preferred for optimum performance at high output frequencies and update rates.

An accurate on-chip 1.2-V temperature compensated bandgap reference and control amplifier allows the user to adjust the full-scale output current from 20 mA down to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage may be applied for maximum flexibility. The device features a SLEEP mode, which reduces the standby power to approximately 10 mW, thereby optimizing the power consumption for the system’s need.

The DAC5674 is available in a 48-pin HTQFP Powerpad™ plastic quad flatpack package. The device is characterized for operation over the industrial temperature range of –40°C to 85°C.

The DAC5674 is a 14-bit resolution high-speed digital-to-analog converter (DAC) with integrated 4x-interpolation filter, on-board clock multiplier, and on-chip voltage reference. The device has been designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct-digital synthesis (DDS) and waveform reconstruction in test and measurement applications.

The 4x-interpolation filter is implemented as a cascade of two 2x-interpolation filters, each of which can be configured for either low-pass or high-pass response. This enables the user to select one of the higher order images present at multiples of the input data rate clock while maintaining a low date input rate. The resulting high IF output frequency allows the user to omit the conventional first mixer in heterodyne transmitter architectures and directly up-convert to RF using only one mixer, thereby reducing system complexity and costs.

In 4x-interpolation low-pass response mode, the DACs excellent spurious free dynamic range (SFDR) at intermediate frequencies located in the first Nyquist zone (up to 40 MHz) allows for multicarrier transmission in cellular base transceiver stations (BTS). The low-pass interpolation mode thereby relaxes image filter requirements by filtering out the images in the adjacent Nyquist zones.

The DAC5674 PLL clock multiplier controls all internal clocks for the digital filters and DAC core. The differential clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock divider of the PLL ensures that the digital filters operate at the correct clock frequencies.

The DAC5674 operates from an analog supply voltage of 3.3 V and a digital supply voltage of 1.8 V. The digital I/Os are 1.8-V and 3.3-V CMOS compatible. Power dissipation is 500 mW at maximum operating conditions. The DAC5674 provides a nominal full-scale differential current-output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The device has been specifically designed for a differential transformer coupled output with a 50- doubly terminated load. For a 20-mA full-scale output current both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2-dBm output power) are supported. The latter configuration is preferred for optimum performance at high output frequencies and update rates.

An accurate on-chip 1.2-V temperature compensated bandgap reference and control amplifier allows the user to adjust the full-scale output current from 20 mA down to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage may be applied for maximum flexibility. The device features a SLEEP mode, which reduces the standby power to approximately 10 mW, thereby optimizing the power consumption for the system’s need.

The DAC5674 is available in a 48-pin HTQFP Powerpad™ plastic quad flatpack package. The device is characterized for operation over the industrial temperature range of –40°C to 85°C.

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기술 문서

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모두 보기8
유형 직함 날짜
* Data sheet 14-Bit 400 MSPS 2x/4x Interpolating CommsDAC DAC datasheet (Rev. A) 2005/10/04
Analog Design Journal Q4 2009 Issue Analog Applications Journal 2018/09/24
Application note Wideband Complementary Current Output DAC Single-Ended Interface (Rev. A) 2015/05/08
Analog Design Journal Interfacing op amps to high-speed DACs, Part 2: Current-sourcing DACs 2009/10/04
Application note Passive Terminations for Current Output DACs 2008/11/10
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008/06/08
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008/06/02
EVM User's guide DAC5674EVM 2002/05/29

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

DAC5674EVM — DAC5674 14비트, 400MSPS, 2x~4x 보간 디지털-아날로그 컨버터 평가 모듈

DAC5674 is an evaluation module for DAC5674, a 400 MSPS digital to analog converter with 2x/4x interpolation. This evaluation module is designed to enable you to evaluate the device under various modes of operation.

사용 설명서: PDF
TI.com에서 구매할 수 없습니다
시뮬레이션 모델

DAC5674 IBIS Model

SLWC061.ZIP (17 KB) - IBIS Model
계산 툴

MATCHGAIN-CALC — 광대역 콤퍼레이터 전류 출력 DAC-SE 인터페이스: 게인 및 규정 준수 전압 스윙에 대한 충돌 일치

NOTE: Calculator software is available when downloading the application note.
  • Click on "abstract" to view abstract of document.
  • Open the ZIP file to extract the calculator tool.
  • Open the PDF file to view the application note.

High-speed digital-to-analog converters (DACs) most often use a (...)

시뮬레이션 툴

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TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
패키지 다운로드
HTQFP (PHP) 48 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
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  • 조립 위치

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