홈 마이크로컨트롤러(MCU) 및 프로세서 DSP(디지털 신호 프로세서)
홈
마이크로컨트롤러(MCU) 및 프로세서
DSP(디지털 신호 프로세서)

DMVA3

마지막 구매

DaVinci 디지털 미디어 프로세서

지금 주문
데이터시트
정오표

DMVA3

마지막 구매
데이터시트 지금 주문

제품 상세 정보

DSP type 0 Operating system Linux, PrOS Ethernet MAC 1 Switch Rating Catalog Operating temperature range (°C) 0 to 0
DSP type 0 Operating system Linux, PrOS Ethernet MAC 1 Switch Rating Catalog Operating temperature range (°C) 0 to 0
FCCSP (AAR) 609 256 mm² 16 x 16
  • High-Performance DaVinci Digital Media Processors
    • Up to 970-MHz ARM® Cortex™-A8 RISC Processor
    • Up to 1940 ARM Cortex-A8 MIPS
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • NEON™ Multimedia Architecture
      • Supports Integer and Floating Point
      • Jazelle® RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32KB of Instruction and Data Caches
    • 256KB of L2 Cache with ECC
    • 64KB of RAM, 48KB of Boot ROM
  • 256KB of On-Chip Memory Controller (OCMC) RAM
  • Imaging Subsystem (ISS)
    • Camera Sensor Connection
      • Parallel Connection for Raw (up to 16-Bit) and BT.656/BT.1120 (8- or 16-Bit)
      • CSI2 Serial Connection
    • Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
    • Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
    • Image Pipe (IPIPE) for Real-Time Image and Video Processing
    • Resizer
      • Resizing Image and Video From 1/16x to 8x
      • Generating Two Different Resizing Outputs Concurrently
      • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
  • Vision Coprocessor
  • Face Detect (FD) Engine
    • Hardware Face Detection for up to 35 Faces Per Frame
  • Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
    • Encode, Decode, Transcode Operations
    • H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4 SP/ASP, JPEG/MJPEG
    • Fourth-Generation Motion-Compensated Noise Filter
  • Media Controller
    • Controls the HDVPSS, HDVICP2, Vision Coprocessor, and ISS
  • Endianness
    • ARM Instructions and Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • Two 165-MHz HD Video Capture Inputs
      • One 16- or 24-Bit Input, Splittable Into Dual 8-Bit SD Capture Ports
      • One 8-, 16-, or 24-Bit HD Input and 8-Bit SD Input Capture Port
    • Two 165-MHz HD Video Display Outputs
      • One 16-, 24-, or 30-Bit and One 16- or 24-Bit Output
    • Component HD Analog Output
    • Composite Analog Output
    • Digital HDMI 1.3 Transmitter with Integrated PHY
    • Advanced Video Processing Features Such as Scan, Format, and Rate Conversion
    • Three Graphics Layers and Compositors
  • 32-Bit DDR2, DDR3, and DDR3L SDRAM Interface
    • Supports up to 400 MHz for DDR2, 533 MHz for DDR3, and 533 MHz for DDR3L
    • Up to Two x 16 Devices, 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
  • General-Purpose Memory Controller (GPMC)
    • 8- or 16-Bit Multiplexed Address and Data Bus
    • 512MB of Total Address Space Divided Among up to 8 Chip Selects
    • Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit or 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and More
  • Enhanced Direct Memory Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels
    • 8 QDMA Channels
  • Ethernet Switch with Dual 10-, 100-, or
    1000-Mbps External Interfaces (EMAC Software)
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • MII/RMII/GMII/RGMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
    • Reset Isolation
    • IEEE 1588 Time-Stamping and Industrial Ethernet Protocols
  • Dual USB 2.0 Ports with Integrated PHYs
    • USB2.0 High- and Full-Speed Clients
    • USB2.0 High-, Full-, and Low-Speed Hosts
    • Supports End Points 0-15
  • One PCI Express 2.0 Port with Integrated PHY
    • Single Port with 1 Lane at 5.0 GT/s
    • Configurable as Root Complex or Endpoint
  • Eight 32-Bit General-Purpose Timers (Timer1–8)
  • One System Watchdog Timer (WDT0)
  • Three Configurable UART/IrDA/CIR Modules
    • UART0 with Modem Control Signals
    • Supports up to 3.6864 Mbps
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • Four Serial Peripheral Interfaces (SPIs) (up to 48 MHz)
    • Each with Four Chip Selects
  • Three MMC/SD/SDIO Serial Interfaces (up to 48 MHz)
    • Supporting up to 1-, 4-, or 8-Bit Modes
  • Dual Controller Area Network (DCAN) Module
    • CAN Version 2 Part A, B
  • Four Inter-Integrated Circuit (I2C Bus™) Ports
  • Two Multichannel Audio Serial Ports (McASP)
    • Six Serializer Transmit and Receive Ports
    • Two Serializer Transmit and Receive Ports
    • DIT-Capable For S/PDIF (All Ports)
  • Four Audio Tracking Logic (ATL) Modules
  • One Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHY
    • Direct Interface to 1 Hard Disk Drive
    • Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
    • Supports Port Multiplier and Command-Based Switching
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 125 General-Purpose I/O (GPIO) Pins
  • One Spin Lock Module with up to 128 Hardware Semaphores
  • One Mailbox Module with 12 Mailboxes
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • SmartReflex™ Technology (Level 2b)
    • Multiple Independent Core Power Domains
    • Multiple Independent Core Voltage Domains
    • Support for Two Operating Points (OPP120 and OPP100) per Voltage Domain
    • Clock Enable and Disable Control for Subsystems and Peripherals
  • 32KB of Embedded Trace Buffer™ (ETB™) and 5-pin Trace Interface for Debug
  • IEEE 1149.1 (JTAG) Compatible
  • 609-Pin Pb-Free BGA Package (AAR Suffix), 0.8-mm Effective Pitch with Via Channel Technology to Reduce PCB Cost (0.5-mm Ball Spacing)
  • 45-nm CMOS Technology
  • 1.8- and 3.3-V Dual Voltage Buffers for General I/O

All trademarks are the property of their respective owners.

  • High-Performance DaVinci Digital Media Processors
    • Up to 970-MHz ARM® Cortex™-A8 RISC Processor
    • Up to 1940 ARM Cortex-A8 MIPS
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • NEON™ Multimedia Architecture
      • Supports Integer and Floating Point
      • Jazelle® RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32KB of Instruction and Data Caches
    • 256KB of L2 Cache with ECC
    • 64KB of RAM, 48KB of Boot ROM
  • 256KB of On-Chip Memory Controller (OCMC) RAM
  • Imaging Subsystem (ISS)
    • Camera Sensor Connection
      • Parallel Connection for Raw (up to 16-Bit) and BT.656/BT.1120 (8- or 16-Bit)
      • CSI2 Serial Connection
    • Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
    • Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
    • Image Pipe (IPIPE) for Real-Time Image and Video Processing
    • Resizer
      • Resizing Image and Video From 1/16x to 8x
      • Generating Two Different Resizing Outputs Concurrently
      • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
  • Vision Coprocessor
  • Face Detect (FD) Engine
    • Hardware Face Detection for up to 35 Faces Per Frame
  • Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
    • Encode, Decode, Transcode Operations
    • H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4 SP/ASP, JPEG/MJPEG
    • Fourth-Generation Motion-Compensated Noise Filter
  • Media Controller
    • Controls the HDVPSS, HDVICP2, Vision Coprocessor, and ISS
  • Endianness
    • ARM Instructions and Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • Two 165-MHz HD Video Capture Inputs
      • One 16- or 24-Bit Input, Splittable Into Dual 8-Bit SD Capture Ports
      • One 8-, 16-, or 24-Bit HD Input and 8-Bit SD Input Capture Port
    • Two 165-MHz HD Video Display Outputs
      • One 16-, 24-, or 30-Bit and One 16- or 24-Bit Output
    • Component HD Analog Output
    • Composite Analog Output
    • Digital HDMI 1.3 Transmitter with Integrated PHY
    • Advanced Video Processing Features Such as Scan, Format, and Rate Conversion
    • Three Graphics Layers and Compositors
  • 32-Bit DDR2, DDR3, and DDR3L SDRAM Interface
    • Supports up to 400 MHz for DDR2, 533 MHz for DDR3, and 533 MHz for DDR3L
    • Up to Two x 16 Devices, 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
  • General-Purpose Memory Controller (GPMC)
    • 8- or 16-Bit Multiplexed Address and Data Bus
    • 512MB of Total Address Space Divided Among up to 8 Chip Selects
    • Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit or 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and More
  • Enhanced Direct Memory Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels
    • 8 QDMA Channels
  • Ethernet Switch with Dual 10-, 100-, or
    1000-Mbps External Interfaces (EMAC Software)
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • MII/RMII/GMII/RGMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
    • Reset Isolation
    • IEEE 1588 Time-Stamping and Industrial Ethernet Protocols
  • Dual USB 2.0 Ports with Integrated PHYs
    • USB2.0 High- and Full-Speed Clients
    • USB2.0 High-, Full-, and Low-Speed Hosts
    • Supports End Points 0-15
  • One PCI Express 2.0 Port with Integrated PHY
    • Single Port with 1 Lane at 5.0 GT/s
    • Configurable as Root Complex or Endpoint
  • Eight 32-Bit General-Purpose Timers (Timer1–8)
  • One System Watchdog Timer (WDT0)
  • Three Configurable UART/IrDA/CIR Modules
    • UART0 with Modem Control Signals
    • Supports up to 3.6864 Mbps
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • Four Serial Peripheral Interfaces (SPIs) (up to 48 MHz)
    • Each with Four Chip Selects
  • Three MMC/SD/SDIO Serial Interfaces (up to 48 MHz)
    • Supporting up to 1-, 4-, or 8-Bit Modes
  • Dual Controller Area Network (DCAN) Module
    • CAN Version 2 Part A, B
  • Four Inter-Integrated Circuit (I2C Bus™) Ports
  • Two Multichannel Audio Serial Ports (McASP)
    • Six Serializer Transmit and Receive Ports
    • Two Serializer Transmit and Receive Ports
    • DIT-Capable For S/PDIF (All Ports)
  • Four Audio Tracking Logic (ATL) Modules
  • One Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHY
    • Direct Interface to 1 Hard Disk Drive
    • Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
    • Supports Port Multiplier and Command-Based Switching
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 125 General-Purpose I/O (GPIO) Pins
  • One Spin Lock Module with up to 128 Hardware Semaphores
  • One Mailbox Module with 12 Mailboxes
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • SmartReflex™ Technology (Level 2b)
    • Multiple Independent Core Power Domains
    • Multiple Independent Core Voltage Domains
    • Support for Two Operating Points (OPP120 and OPP100) per Voltage Domain
    • Clock Enable and Disable Control for Subsystems and Peripherals
  • 32KB of Embedded Trace Buffer™ (ETB™) and 5-pin Trace Interface for Debug
  • IEEE 1149.1 (JTAG) Compatible
  • 609-Pin Pb-Free BGA Package (AAR Suffix), 0.8-mm Effective Pitch with Via Channel Technology to Reduce PCB Cost (0.5-mm Ball Spacing)
  • 45-nm CMOS Technology
  • 1.8- and 3.3-V Dual Voltage Buffers for General I/O

All trademarks are the property of their respective owners.

DMVA3 and DMVA4 DaVinci Digital Media Processors are a highly integrated, cost-effective, low-power, programmable platform that leverages TI’s DaVinci processor technology to meet the processing needs of multichannel Digital Video Recorders (DVR), Network Video Recorders (NVR), HD Video Conferencing - Skype endpoints, IP Netcam, Digital Signage, Media Players and Adapters, Mobile Medical Imaging, Network Projectors, Home Audio and Video Equipment, and similar devices in SD and HD resolutions. The Programmable High-Definition Video Image Processor of the device supports 1080p60 or more than 8 channels of D1 real time H.264BP/MP/HP video encode or decode. The included best-in-class H.264 encoder provides high-quality video encode for the lowest possible bit rate under all conditions, reducing valuable storage space to a minimum. In addition, the device also supports other video codecs such as MJPEG, MPEG-2, and MPEG-4. The device provides a full set of video preprocessing and postprocessing functions to ensure the best video quality. The low power consumption and high performance of the device makes it particularly suitable for portable and automotive applications. The DMVA3/4 are uniquely capable of running the Fourth-Generation Motion-Compensated Noise Filtering technology of TI.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.

The device processors include a high-definition video and imaging coprocessor 2 (HDVICP2), to off-load many video and imaging processing tasks for common video and imaging algorithms. In addition, the devices include a custom vision coprocessor with an available suite of TI-developed video analytics functions. Programmability is provided by an ARM Cortex-A8 RISC CPU with NEON extension and high-definition video and imaging coprocessors. The ARM lets developers separate control functions from A/V algorithms programmed on coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache with ECC; 48KB of boot ROM; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem; Dual-Port Gigabit Ethernet MACs (10/100/1000 Mbps) (Ethernet Switch) with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, and Industrial Ethernet Protocols; two USB ports with integrated 2.0 PHY; PCIe x1 GEN2-Compliant interface; two serializer McASP audio serial ports (with DIT mode); three UARTs with IrDA and CIR support; four SPI serial interfaces; a CSI2 serial connection; three MMC/SD/SDIO serial interfaces; four I2C master and slave interfaces; a parallel camera interface (CAM); a vision coprocessor; up to 125 general-purpose I/Os (GPIOs); eight 32-bit general-purpose timers; system watchdog timer; DDR2/DDR3/DDR3L SDRAM interface; flexible 8- or 16-bit asynchronous memory interface; two Controller Area Network (DCAN) modules; one Serial ATA (SATA) 3.0 Gbps controller with integrated PHY; a Spin Lock; and Mailbox.

Additionally, TI provides a complete set of development tools for the ARM which include C compilers and a Microsoft® Windows® debugger interface for visibility into source code execution.

DMVA3 and DMVA4 DaVinci Digital Media Processors are a highly integrated, cost-effective, low-power, programmable platform that leverages TI’s DaVinci processor technology to meet the processing needs of multichannel Digital Video Recorders (DVR), Network Video Recorders (NVR), HD Video Conferencing - Skype endpoints, IP Netcam, Digital Signage, Media Players and Adapters, Mobile Medical Imaging, Network Projectors, Home Audio and Video Equipment, and similar devices in SD and HD resolutions. The Programmable High-Definition Video Image Processor of the device supports 1080p60 or more than 8 channels of D1 real time H.264BP/MP/HP video encode or decode. The included best-in-class H.264 encoder provides high-quality video encode for the lowest possible bit rate under all conditions, reducing valuable storage space to a minimum. In addition, the device also supports other video codecs such as MJPEG, MPEG-2, and MPEG-4. The device provides a full set of video preprocessing and postprocessing functions to ensure the best video quality. The low power consumption and high performance of the device makes it particularly suitable for portable and automotive applications. The DMVA3/4 are uniquely capable of running the Fourth-Generation Motion-Compensated Noise Filtering technology of TI.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.

The device processors include a high-definition video and imaging coprocessor 2 (HDVICP2), to off-load many video and imaging processing tasks for common video and imaging algorithms. In addition, the devices include a custom vision coprocessor with an available suite of TI-developed video analytics functions. Programmability is provided by an ARM Cortex-A8 RISC CPU with NEON extension and high-definition video and imaging coprocessors. The ARM lets developers separate control functions from A/V algorithms programmed on coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache with ECC; 48KB of boot ROM; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem; Dual-Port Gigabit Ethernet MACs (10/100/1000 Mbps) (Ethernet Switch) with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, and Industrial Ethernet Protocols; two USB ports with integrated 2.0 PHY; PCIe x1 GEN2-Compliant interface; two serializer McASP audio serial ports (with DIT mode); three UARTs with IrDA and CIR support; four SPI serial interfaces; a CSI2 serial connection; three MMC/SD/SDIO serial interfaces; four I2C master and slave interfaces; a parallel camera interface (CAM); a vision coprocessor; up to 125 general-purpose I/Os (GPIOs); eight 32-bit general-purpose timers; system watchdog timer; DDR2/DDR3/DDR3L SDRAM interface; flexible 8- or 16-bit asynchronous memory interface; two Controller Area Network (DCAN) modules; one Serial ATA (SATA) 3.0 Gbps controller with integrated PHY; a Spin Lock; and Mailbox.

Additionally, TI provides a complete set of development tools for the ARM which include C compilers and a Microsoft® Windows® debugger interface for visibility into source code execution.
open-in-new 기타 DSP(디지털 신호 프로세서) 찾기
다운로드 스크립트와 함께 비디오 보기 동영상

타사를 통한 지원

이 제품은 TI에서 지속적으로 직접 설계 지원을 제공하지 않습니다. 설계 작업 중 지원을 받으려면 다음 타사 중 하나에 문의할 수 있습니다. D3 Engineering, elnfochips, Ittiam Systems, Path Partner Technology 또는 Z3 Technologies.

기술 문서

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
모두 보기2
유형 직함 날짜
* Data sheet DMVA3 and DMVA4 DaVinci Digital Media Processor datasheet (Rev. B) 2013/12/18
* Errata DMVA3 and DMVA4 DaVinci Digital Media Processor SE (Silicon Rev. 1.1, 1.0) (Rev. A) 2013/12/18

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 디바이스 디버깅에 사용되는 디버그 프로브(에뮬레이터)입니다. XDS200은 저렴한 XDS110 및 고성능 XDS560v2에 비해 저렴한 비용으로 우수한 성능을 균형 있게 제공합니다. 단일 포드에서 광범위한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 (...)

TI.com에서 구매할 수 없습니다
디버그 프로브

TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

TI.com에서 구매할 수 없습니다
디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

TI.com에서 구매할 수 없습니다
설계 툴

PROCESSORS-3P-SEARCH — Arm 기반 MPU, arm 기반 MCU 및 DSP 타사 검색 툴

TI는 여러 회사와의 협력을 통해 TI 프로세서를 사용하여 광범위한 소프트웨어, 툴 및 SOM을 제공해서 생산 단계로 가는 속도를 높이고 있습니다. 이 검색 툴을 다운로드하여 타사 솔루션을 빠르게 검색하고 필요에 맞는 올바른 타사를 찾아보세요. 여기에 나열된 소프트웨어, 툴 및 모듈은 텍사스 인스트루먼트가 아닌 독립적인 타사에서 생산 및 관리하고 있습니다.

검색 툴은 다음과 같이 제품 유형별로 분류되어 있습니다.

  • 툴에는 IDE/컴파일러, 디버그 및 추적, 시뮬레이션 및 모델링 소프트웨어, 플래시 프로그래머가 포함되어 있습니다.
  • OS에는 (...)
다운로드
패키지 핀 다운로드
FCCSP (AAR) 609 옵션 보기
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상