홈 스위치 및 멀티플렉서 아날로그 스위치 및 멀티플렉서
홈
스위치 및 멀티플렉서
아날로그 스위치 및 멀티플렉서

SN74CBTLV3257-EP

활성

EP(Enhanced Product) 저압 4비트 1/2 FET 멀티플렉서/디멀티플렉서

지금 주문
데이터시트

SN74CBTLV3257-EP

활성
데이터시트 지금 주문

제품 상세 정보

Configuration 2:1 SPDT Number of channels 4 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Ron (typ) (Ω) 5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -55 to 125 Features Powered-off protection Input/output continuous current (max) (mA) 128 Rating HiRel Enhanced Product Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
Configuration 2:1 SPDT Number of channels 4 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Ron (typ) (Ω) 5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -55 to 125 Features Powered-off protection Input/output continuous current (max) (mA) 128 Rating HiRel Enhanced Product Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
TSSOP (PW) 16 32 mm² 5 x 6.4
  • Controlled baseline
    • One assembly site
    • One test site
    • One fabrication site
  • Extended temperature performance of –55°C to 125°C
  • Enhanced diminishing manufacturing sources (DMS) support
  • Enhanced product-change notification
  • Qualification pedigree (1)
  • 5-Ω switch connection between two ports
  • Rail-to-rail switching on data I/O ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000-V human-body model (A114-A)
    • 200-V machine model (A115-A)

(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled baseline
    • One assembly site
    • One test site
    • One fabrication site
  • Extended temperature performance of –55°C to 125°C
  • Enhanced diminishing manufacturing sources (DMS) support
  • Enhanced product-change notification
  • Qualification pedigree (1)
  • 5-Ω switch connection between two ports
  • Rail-to-rail switching on data I/O ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000-V human-body model (A114-A)
    • 200-V machine model (A115-A)

(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The SN74CBTLV3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when the output-enable (OE) input is high.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current does not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when the output-enable (OE) input is high.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current does not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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기술 문서

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모두 보기18
유형 직함 날짜
* Data sheet SN74CBTLV3257-EP Low-Voltage 4-Bit 1-of-2 FET Multiplexer/Demultiplexer datasheet (Rev. A) PDF | HTML 2019/05/06
* VID SN74CBTLV3257-EP VID V6208615 2016/06/21
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022/06/02
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021/12/01
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
More literature Digital Bus Switch Selection Guide (Rev. A) 2004/11/10
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Bus FET Switch Solutions for Live Insertion Applications 2003/02/07
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) 1998/12/01

설계 및 개발

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패키지 핀 다운로드
TSSOP (PW) 16 옵션 보기
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

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