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스위치 및 멀티플렉서
디지탈 디멀티플렉서 및 디코더

SN74HC139-Q1

활성

오토모티브 카탈로그 듀얼 2라인-4라인 디코더/디멀티플렉서

지금 주문
데이터시트

SN74HC139-Q1

활성
데이터시트 지금 주문

제품 상세 정보

Technology family HC Number of channels 2 Operating temperature range (°C) -40 to 125 Rating Automotive Supply current (max) (µA) 80
Technology family HC Number of channels 2 Operating temperature range (°C) -40 to 125 Rating Automotive Supply current (max) (µA) 80
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Qualified for Automotive Applications
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive up to Ten LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 10 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
  • ESD Protection Level per AEC-Q100 Classification
    • 2000-V (H2) Human-Body Model
    • 200-V (M3) Machine Model
    • 1000-V (C5) Charged-Device Model
  • Qualified for Automotive Applications
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive up to Ten LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 10 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
  • ESD Protection Level per AEC-Q100 Classification
    • 2000-V (H2) Human-Body Model
    • 200-V (M3) Machine Model
    • 1000-V (C5) Charged-Device Model

The SN74HC139 device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The SN74HC139 device comprises two individual 2-line to 4-line decoders in a single package. The active-low enable G input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit.

The SN74HC139 device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The SN74HC139 device comprises two individual 2-line to 4-line decoders in a single package. The active-low enable G input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit.
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기술 문서

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모두 보기15
유형 직함 날짜
* Data sheet Dual 2-Line to 4-Line Decoder/Demultiplexer datasheet (Rev. B) 2008/04/24
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
More literature Automotive Logic Devices Brochure 2014/08/27
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996/05/01
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996/04/01

설계 및 개발

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평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

사용 설명서: PDF | HTML
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패키지 핀 다운로드
SOIC (D) 16 옵션 보기
TSSOP (PW) 16 옵션 보기
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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