인터페이스 I2C & I3C ICs I2C & I3C level shifters, buffers & hubs

TCA9517A

활성

전원 끔 고임피던스를 갖춘 2비트 레벨 변환 400kHz I2C/SMBus 버퍼/리피터

제품 상세 정보

Features Buffer, Enable pin Protocols I2C Frequency (max) (MHz) 0.4 VCCA (min) (V) 0.9 VCCA (max) (V) 5.5 VCCB (min) (V) 2.7 VCCB (max) (V) 5.5 Supply restrictions VCCA <= VCCB Rating Catalog Operating temperature range (°C) -40 to 85
Features Buffer, Enable pin Protocols I2C Frequency (max) (MHz) 0.4 VCCA (min) (V) 0.9 VCCA (max) (V) 5.5 VCCB (min) (V) 2.7 VCCB (max) (V) 5.5 Supply restrictions VCCA <= VCCB Rating Catalog Operating temperature range (°C) -40 to 85
VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Two-Channel Bidirectional Buffer
  • I2C Bus and SMBus Compatible
  • Operating Supply Voltage Range of 0.9 V to 5.5 V on A-side
  • Operating Supply Voltage Range of 2.7 V to 5.5 V on B-side
  • Voltage-Level Translation From 0.9 V - 5.5 V to 2.7 V - 5.5 V
  • Footprint and Functional Replacement for PCA9515B
  • Active-High Repeater-Enable Input
  • Open-Drain I2C I/O
  • 5.5-V Tolerant I2C and Enable Input Support Mixed-Mode Signal Operation
  • Accommodates Standard Mode and Fast Mode I2C Devices and Multiple Masters
  • High-Impedance I2C Pins When Powered-Off
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 5500 V Human-Body Model (A114-A)
    • 200 V Machine Model (A115-A)
    • 1000 V Charged-Device Model (C101)
  • Two-Channel Bidirectional Buffer
  • I2C Bus and SMBus Compatible
  • Operating Supply Voltage Range of 0.9 V to 5.5 V on A-side
  • Operating Supply Voltage Range of 2.7 V to 5.5 V on B-side
  • Voltage-Level Translation From 0.9 V - 5.5 V to 2.7 V - 5.5 V
  • Footprint and Functional Replacement for PCA9515B
  • Active-High Repeater-Enable Input
  • Open-Drain I2C I/O
  • 5.5-V Tolerant I2C and Enable Input Support Mixed-Mode Signal Operation
  • Accommodates Standard Mode and Fast Mode I2C Devices and Multiple Masters
  • High-Impedance I2C Pins When Powered-Off
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 5500 V Human-Body Model (A114-A)
    • 200 V Machine Model (A115-A)
    • 1000 V Charged-Device Model (C101)

The TCA9517A is a bidirectional buffer with level shifting capabilities for I2C and SMBus systems. It provides bidirectional voltage-level translation (up-translation/down-translation) between low voltages (down to 0.9 V) and higher voltages (2.7 V to 5.5 V) in mixed-mode applications. This device enables I2C and SMBus systems to be extended without degradation of performance, even during level shifting.

The TCA9517A buffers both the serial data (SDA) and the serial clock (SCL) signals on the I2C bus, thus allowing two buses of up to 400-pF bus capacitance to be connected in an I2C application.

The TCA9517A has two types of drivers: A-side drivers and B-side drivers. All inputs and I/Os are over-voltage tolerant to 5.5 V, even when the device is unpowered (VCCB and/or VCCA = 0 V).

The TCA9517A offers a higher contention level threshold, VILC, than the TCA9517, which allows connections to slaves which have weaker pulldown ability.

The type of buffer design on the B-side prevents it from being used in series with devices which use static voltage offset. This is because these devices do not recognize buffered low signals as a valid low and do not propagate it as a buffered low again.

The B-side drivers operate from 2.7 V to 5.5 V. The output low level for this internal buffer is approximately 0.5 V, but the input voltage must be 70 mV or more below the output low level when the output internally is driven low. The higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not recognized as a low by the input. This feature prevents a lockup condition from occurring when the input low condition is released.

The A-side drivers operate from 0.9 V to 5.5 V and drive more current. They do not require the buffered low feature (or the static offset voltage). This means that a low signal on the B-side translates to a nearly 0 V low on the A-side, which accommodates smaller voltage swings of lower-voltage logic. The output pulldown on the A-side drives a hard low, and the input level is set at 0.3 × VCCA to accommodate the need for a lower low level in systems where the low-voltage-side supply voltage is as low as 0.9 V.

The A-side of two or more TCA9517As can be connected together, allowing many topographies (See Figure 8 and Figure 9 ), with the A-side as the common bus. Also, the A-side can be connected directly to any other buffer with static- or dynamic-offset voltage. Multiple TCA9517As can be connected in series, A-side to B-side, with no buildup in offset voltage and with only time-of-flight delays to consider. The TCA9517A cannot be connected B-side to B-side, because of the buffered low voltage from the B-side. The B-side cannot be connected to a device with rise time accelerators.

VCCA is only used to provide the 0.3 × VCCA reference to the A-side input comparators and for the power-good-detect circuit. The TCA9517A logic and all I/Os are powered by the VCCB pin.

As with the standard I2C system, pullup resistors are required to provide the logic-high levels on the buffered bus. The TCA9517A has standard open-drain configuration of the I2C bus. The size of these pullup resistors depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to work with Standard mode and Fast mode I2C devices in addition to SMBus devices. Standard mode I2C devices only specify 3 mA in a generic I2C system, where Standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used.

The TCA9517A is a bidirectional buffer with level shifting capabilities for I2C and SMBus systems. It provides bidirectional voltage-level translation (up-translation/down-translation) between low voltages (down to 0.9 V) and higher voltages (2.7 V to 5.5 V) in mixed-mode applications. This device enables I2C and SMBus systems to be extended without degradation of performance, even during level shifting.

The TCA9517A buffers both the serial data (SDA) and the serial clock (SCL) signals on the I2C bus, thus allowing two buses of up to 400-pF bus capacitance to be connected in an I2C application.

The TCA9517A has two types of drivers: A-side drivers and B-side drivers. All inputs and I/Os are over-voltage tolerant to 5.5 V, even when the device is unpowered (VCCB and/or VCCA = 0 V).

The TCA9517A offers a higher contention level threshold, VILC, than the TCA9517, which allows connections to slaves which have weaker pulldown ability.

The type of buffer design on the B-side prevents it from being used in series with devices which use static voltage offset. This is because these devices do not recognize buffered low signals as a valid low and do not propagate it as a buffered low again.

The B-side drivers operate from 2.7 V to 5.5 V. The output low level for this internal buffer is approximately 0.5 V, but the input voltage must be 70 mV or more below the output low level when the output internally is driven low. The higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not recognized as a low by the input. This feature prevents a lockup condition from occurring when the input low condition is released.

The A-side drivers operate from 0.9 V to 5.5 V and drive more current. They do not require the buffered low feature (or the static offset voltage). This means that a low signal on the B-side translates to a nearly 0 V low on the A-side, which accommodates smaller voltage swings of lower-voltage logic. The output pulldown on the A-side drives a hard low, and the input level is set at 0.3 × VCCA to accommodate the need for a lower low level in systems where the low-voltage-side supply voltage is as low as 0.9 V.

The A-side of two or more TCA9517As can be connected together, allowing many topographies (See Figure 8 and Figure 9 ), with the A-side as the common bus. Also, the A-side can be connected directly to any other buffer with static- or dynamic-offset voltage. Multiple TCA9517As can be connected in series, A-side to B-side, with no buildup in offset voltage and with only time-of-flight delays to consider. The TCA9517A cannot be connected B-side to B-side, because of the buffered low voltage from the B-side. The B-side cannot be connected to a device with rise time accelerators.

VCCA is only used to provide the 0.3 × VCCA reference to the A-side input comparators and for the power-good-detect circuit. The TCA9517A logic and all I/Os are powered by the VCCB pin.

As with the standard I2C system, pullup resistors are required to provide the logic-high levels on the buffered bus. The TCA9517A has standard open-drain configuration of the I2C bus. The size of these pullup resistors depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to work with Standard mode and Fast mode I2C devices in addition to SMBus devices. Standard mode I2C devices only specify 3 mA in a generic I2C system, where Standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used.

다운로드 스크립트와 함께 비디오 보기 동영상

기술 문서

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
모두 보기7
유형 직함 날짜
* Data sheet TCA9517A Level-Shifting I2C Bus Repeater datasheet (Rev. C) PDF | HTML 2018/12/05
Application note Resolving Improper Implementation of the Static Voltage Offset on I2C Buffers PDF | HTML 2023/10/09
Application note Why, When, and How to use I2C Buffers 2018/05/23
Application note Choosing the Correct I2C Device for New Designs PDF | HTML 2016/09/07
Application note Understanding the I2C Bus PDF | HTML 2015/06/30
Application note Maximum Clock Frequency of I2C Bus Using Repeaters 2015/05/15
Application note I2C Bus Pull-Up Resistor Calculation PDF | HTML 2015/02/13

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 모델

TCA9517A IBIS Model

SCPM026.ZIP (46 KB) - IBIS Model
설계 툴

I2C-DESIGNER — I2C 디자이너 툴

Use the I2C Designer tool to quickly resolve conflicts in addressing, voltage level and frequency in I2C based designs. Enter master and slave inputs to automatically generate an I2C tree or easily build a custom solution. This tool will help designers save time and comply with the I2C standard (...)
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
레퍼런스 디자인

PMP23365 — 외부 핫 스왑 및 원격 측정을 지원하는 24V, 3A 클래스 8 PoE PD 레퍼런스 설계

이 레퍼런스 설계는 24V 및 3A 출력을 지원하는 PoE(Power over Ethernet) PD(Power Device) 능동 클램프 순방향 컨버터를 구현합니다. PWM(펄스 폭 모듈레이터) 컨트롤러가 통합된 TPS23730 PD는 능동 클램프 순방향 컨버터를 위한 PoE PD 제어 및 PWM 제어에 필요한 모든 기능을 제공합니다. 이 설계는 옵토커플러 피드백과 함께 2차측 조정(SSR)을 사용합니다. 클래스 7 및 8 PD 애플리케이션을 활성화하기 위해 외부 핫 스왑이 추가되었습니다. INA237은 1차측 DC/DC 입력 (...)
Test report: PDF
패키지 다운로드
VSSOP (DGK) 8 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상