TL16C554
- Integrated Asynchronous Communications Element
- Consists of Four Improved TL16C550 ACEs Plus Steering Logic
- In FIFO Mode, Each ACE Transmitter and Receiver Is Buffered With 16-Byte FIFO to Reduce the Number of Interrupts to CPU
- In TL16C450 Mode, Hold and Shift Registers Eliminate Need for Precise Synchronization Between the CPU and Serial Data
- Up to 16-MHz Clock Rate for up to 1-Mbaud Operation
- Programmable Baud Rate Generators Which Allow Division of Any Input Reference Clock by 1 to (216-1) and Generate an Internal 16 × Clock
- Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial Data Stream
- Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts
- Fully Programmable Serial Interface Characteristics:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit
- 1-, 1 1/2-, or 2-Stop Bit Generation
- Baud Generation (DC to 1-Mbit Per Second)
- False Start Bit Detection
- Complete Status Reporting Capabilities
- Line Break Generation and Detection
- Internal Diagnostic Capabilities:
- Loopback Controls for Communications Link Fault Isolation
- Break, Parity, Overrun, Framing Error Simulation
- Fully Prioritized Interrupt System Controls
- Modem Control Functions (CTS\, RTS\, DSR\, DTR\, RI\, and DCD\)
- 3-State Outputs Provide TTL Drive Capabilities for Bidirectional Data Bus and Control Bus
The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous communications element (ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional operation by the CPU. The information obtained includes the type and condition of the operation performed and any error conditions encountered.
The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on the chip. Two terminal functions allow signaling of direct memory access (DMA) transfers. Each ACE includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216-1).
The TL16C554 and the TL16C554I are available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and in an 80-pin (TQFP) PN package.
기술 문서
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | Asynchronous-Communications Element datasheet (Rev. G) | 2006/03/02 |
설계 및 개발
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| 패키지 | 핀 | 다운로드 |
|---|---|---|
| LQFP (PN) | 80 | 옵션 보기 |
| PLCC (FN) | 68 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치