홈 인터페이스 UART
홈
인터페이스
UART

TL16C752B-EP

활성

64바이트 FIFO를 지원하는 향상된 제품 3.3V 듀얼 UART

지금 주문
데이터시트
정오표

TL16C752B-EP

활성
데이터시트 지금 주문

제품 상세 정보

Number of channels 2 FIFO (Byte) 64 Rx FIFO trigger levels (#) 16 Tx FIFO trigger levels (#) 16 Programmable FIFO trigger levels Yes CPU interface X86 Baud rate at Vcc = 2.5 V & with 16x sampling (max) (MBps) 1.5 Baud rate at Vcc = 1.8 V & with 16x sampling (max) (MBps) 1 Baud rate at Vcc = 3.3 V & with 16x sampling (max) (MBps) 2 Baud rate at Vcc = 5 V & with 16x sampling (max) (MBps) 3 Operating voltage (V) 3.3 Auto RTS/CTS Yes Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 110
Number of channels 2 FIFO (Byte) 64 Rx FIFO trigger levels (#) 16 Tx FIFO trigger levels (#) 16 Programmable FIFO trigger levels Yes CPU interface X86 Baud rate at Vcc = 2.5 V & with 16x sampling (max) (MBps) 1.5 Baud rate at Vcc = 1.8 V & with 16x sampling (max) (MBps) 1 Baud rate at Vcc = 3.3 V & with 16x sampling (max) (MBps) 2 Baud rate at Vcc = 5 V & with 16x sampling (max) (MBps) 3 Operating voltage (V) 3.3 Auto RTS/CTS Yes Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 110
LQFP (PT) 48 81 mm² 9 x 9
  • Controlled Baseline
    • One Assembly Site
    • Test Site
    • One Fabrication Site
  • Extended Temperature Performance of\
    –55°C to 110°C and –40°C to 105°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree(1)
  • Pin Compatible With ST16C2550 With Additional Enhancements
  • Up to 1.5-Mbps Baud Rate When Using Crystal (24-MHz Input Clock)
  • Up to 3-Mbps Baud Rate When Using Oscillator or Clock Source (48-MHz Input Clock)
  • 64-Byte Transmit FIFO
  • 64-Byte Receive FIFO With Error Flags
  • Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA and Interrupt Generation
  • Programmable Receive FIFO Trigger Levels for Software/Hardware Flow Control
  • Software/Hardware Flow Control
    • Programmable Xon/Xoff Characters
    • Programmable Auto-RTS and Auto-CTS
  • Optional Data Flow Resume by Xon Any Character
  • DMA Signaling Capability for Both Received and Transmitted Data
  • Supports 3.3-V Operation
  • Software Selectable Baud Rate Generator
  • Prescaler Provides Additional Divide By Four Function
  • Fast Access Time 2 Clock Cycle IOR/IOW Pulse Width
  • Programmable Sleep Mode
  • Programmable Serial Interface Characteristics
    • 5-Bit, 6-Bit, 7-Bit, or 8-Bit Characters
    • Even, Odd, or No Parity Bit Generation and Detection
    • 1, 1.5, or 2 Stop Bit Generation
  • False Start Bit Detection
  • Complete Status Reporting Capabilities in Both Normal and Sleep Mode
  • Line Break Generation and Detection
  • Internal Test and Loopback Capabilities
  • Fully Prioritized Interrupt System Controls
  • Modem Control Functions (CTS, RTS, DSR, DTR, RI, and CD)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly Site
    • Test Site
    • One Fabrication Site
  • Extended Temperature Performance of\
    –55°C to 110°C and –40°C to 105°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree(1)
  • Pin Compatible With ST16C2550 With Additional Enhancements
  • Up to 1.5-Mbps Baud Rate When Using Crystal (24-MHz Input Clock)
  • Up to 3-Mbps Baud Rate When Using Oscillator or Clock Source (48-MHz Input Clock)
  • 64-Byte Transmit FIFO
  • 64-Byte Receive FIFO With Error Flags
  • Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA and Interrupt Generation
  • Programmable Receive FIFO Trigger Levels for Software/Hardware Flow Control
  • Software/Hardware Flow Control
    • Programmable Xon/Xoff Characters
    • Programmable Auto-RTS and Auto-CTS
  • Optional Data Flow Resume by Xon Any Character
  • DMA Signaling Capability for Both Received and Transmitted Data
  • Supports 3.3-V Operation
  • Software Selectable Baud Rate Generator
  • Prescaler Provides Additional Divide By Four Function
  • Fast Access Time 2 Clock Cycle IOR/IOW Pulse Width
  • Programmable Sleep Mode
  • Programmable Serial Interface Characteristics
    • 5-Bit, 6-Bit, 7-Bit, or 8-Bit Characters
    • Even, Odd, or No Parity Bit Generation and Detection
    • 1, 1.5, or 2 Stop Bit Generation
  • False Start Bit Detection
  • Complete Status Reporting Capabilities in Both Normal and Sleep Mode
  • Line Break Generation and Detection
  • Internal Test and Loopback Capabilities
  • Fully Prioritized Interrupt System Controls
  • Modem Control Functions (CTS, RTS, DSR, DTR, RI, and CD)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The TL16C752B is a dual-universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 3 Mbps. The TL16C752B offers enhanced features. It has a transmission control register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and has software flow control and hardware flow control capabilities.

The TL16C752B is available in a 48-pin PT (LQFP) package.

The TL16C752B is a dual-universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 3 Mbps. The TL16C752B offers enhanced features. It has a transmission control register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and has software flow control and hardware flow control capabilities.

The TL16C752B is available in a 48-pin PT (LQFP) package.
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기술 문서

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모두 보기3
유형 직함 날짜
* Data sheet 3.3-V Dual UART With 64-Byte FIFO datasheet (Rev. B) 2007/12/10
* Errata TL16C752B Errata 2006/08/03
* VID TL16C752B-EP VID V6203626 2016/06/21

설계 및 개발

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시뮬레이션 툴

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TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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